Datasheet ADAU1701 (Analog Devices) - 37

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Data Sheet ADAU1701 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD
After the address and data registers are loaded, set the initiate
DATA REGISTERS
safeload transfer bit in the core control register to initiate the loading into RAM. Each of the five safeload registers takes one of Many applications require real-time microcontroller control of the 1024 core instructions to load into the parameter RAM. The signal processing parameters, such as filter coefficients, mixer total program lengths should, therefore, be limited to 1019 cycles gains, multichannel virtualizing parameters, or dynamics (1024 minus 5) to ensure that the SigmaDSP core always has at processing curves. When controlling a biquad filter, for least five cycles available. The safeload is guaranteed to occur example, all of the parameters must be updated at the same within one LRCLK period (21 μs for a f time. Doing so prevents the filter from executing with a mix of S of 48 kHz) of the initiate safeload transfer bit being set. old and new coefficients for one or two audio frames, thus avoiding temporary instability and transients that may take a The safeload logic automatically sends data to be loaded into long time to decay. To accomplish this, the ADAU1701 uses RAM from only those safeload registers that have been written safeload data registers to simultaneously load a set of five 28-bit to since the last safeload operation. For example, if two parameters values to the desired parameter RAM address. Five registers are are to be updated in the RAM, only two of the five safeload registers used because a biquad filter uses five coefficients and, as must be written. When the initiate safeload transfer bit is asserted, previously mentioned, it is desirable to do a complete update in only data from those two registers are sent to the RAM; the other one transaction. three registers are not sent to the RAM and may hold old or invalid data. The first step in performing a safeload operation is writing the parameter address to one of the safeload address registers (2069
Table 38. Safeload Address and Data Register Mapping
to 2073). The 10-bit data-word to be written is the address in
Safeload Safeload Safeload
parameter RAM to which the safeload is being performed. After
Register Address Register Data Register
this address is written, the 28-bit data-word can be written to 0 2069 2064 the corresponding safeload data register (2064 to 2068). 1 2070 2065 The data formats for these writes are detailed in Table 29 and 2 2071 2066 Table 30. Table 38 shows how each of the five address registers 3 2072 2067 maps to its corresponding data register. 4 2073 2068
Table 39. Safeload Registers Bit Map D39 D38 D37 D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
SD39 SD38 SD37 SD36 SD35 SD34 SD33 SD32 0x00 SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 SD19 SD18 SD17 SD16 0x0000 SD15 SD14 SD13 SD12 SD11 SD10 SD09 SD08 SD07 SD06 SD05 SD04 SD03 SD02 SD01 SD00 0x0000
Table 40. Bit Name Description
SD[39:0] Safeload Data. Data (program, parameters, register contents) to be loaded into the RAMs or registers.
2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS Table 41. Safeload Address Registers Bit Map D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0 0 0 0 SA11 SA10 SA09 SA08 SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 0x0000
Table 42. Bit Name Description
SA[11:0] Safeload Address. Address of data that is to be loaded into the RAMs or registers Rev. C | Page 37 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER TEMPERATURE RANGE PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS 2056 (0x0808)—GPIO PIN SETTING REGISTER 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS 2076 (0x081C)—DSP CORE CONTROL REGISTER 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL 2084 (0x0824)—AUXILIARY ADC ENABLE 2086 (0x0826)—OSCILLATOR POWER-DOWN 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE