Datasheet ACS71020 (Allegro) - 6

制造商Allegro
描述Single Phase, Isolated, Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection
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Single Phase, Isolated, Power Monitoring IC. ACS71020 with Voltage Zero Crossing and Overcurrent Detection

Single Phase, Isolated, Power Monitoring IC ACS71020 with Voltage Zero Crossing and Overcurrent Detection

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Single Phase, Isolated, Power Monitoring IC ACS71020 with Voltage Zero Crossing and Overcurrent Detection COMMON ELECTRICAL CHARACTERISTICS [1]:
Valid through the full range of TA and VCC = VCC(nom), unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit ELECTRICAL CHARACTERISTICS
Supply Voltage VCC VCC(nom) × 0.9 VCC(nom) VCC(nom) × 1.1 V Supply Current I VCC(min) ≤ VCC ≤ VCC(max), no load CC on output pins – 12 14 mA
VOLTAGE BUFFER
Differential Input Range ΔVIN VINP – VINN –275 – 275 mV 2 2 Common Mode Input Voltage V /3 × VCC /3 × VCC IN(CM) – 0.275 – + 0.275 V
VOLTAGE ADC
Sample Frequency fS – 32 – kHz Number of Bits NADC(V) – 16 – bits Voltage ADC Power Supply Rejection V_PSRR Ratio of change on VCC to change in ADC internal reference at DC 60 70 – dB
VOLTAGE SIGNAL CHAIN
Noise VN – 10 – LSB Internal Bandwidth BW – 1 – kHz Linearity Error ELIN – ±0.2 – %
CURRENT CHANNEL ADC
Sample Frequency fS – 32 – kHz Number of Bits NADC(I) – 16 – bits Current Channel ADC Power Supply Rejection I_PSRR Ratio of change on VCC to change in ADC internal reference at DC 60 70 – dB
CURRENT CHANNEL
Internal Bandwidth BW – 1 – kHz Primary Conductor Resistance RIP TA = 25°C – 0.85 – mΩ Noise VN – 100 – LSB Linearity Error ELIN – ±1.5 – %
OVERCURRENT FAULT CHARACTERISTICS
Time from IP rising above IFAULT until VFAULT < VFAULT(max) for a current Fault Response Time tRF step from 0 to 1.2 × IFAULT; 10 kΩ and – 5 – μs 100 pF from DIO_1 to ground; fltdly set to 0 Internal Bandwidth BW – 200 – kHz Fault Hysteresis [2] IHYST – 0.05 × IPR – A Fault Range IFAULT Set using FAULT field in EEPROM 0.5 × IPR – 1.75 × IPR A
VOLTAGE ZERO CROSSING
Voltage Zero Crossing Delay td – 700 µs [1] Device may be operated at higher primary current levels, IP, ambient, TA, and internal leadframe temperatures, TA, provided that the Maximum Junction Temperature, TJ(max), is not exceeded. [2] After IP goes above IFAULT, tripping the internal fault comparator, IP must go below IFAULT – IHYST, before the internal fault comparator will reset. Continued on next page... Allegro MicroSystems, LLC 6 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Selection Guide Absolute Maximum Ratings Isolation Characteristics Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Digital I/O Electrical Characteristics Data Acquisition ADCs Raw Signal Sensitivity and Offset Trim Phase Compensation Zero Crossing Power Calculations Digital Communication Registers and EEPROM EEPROM Error Checking and Correction (ECC) Memory Map Volatile Memory Map Application Connections Recommended PCB Layout Package Outline Drawing