Datasheet ACS71020 (Allegro) - 7
| 制造商 | Allegro |
| 描述 | Single Phase, Isolated, Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection |
| 页数 / 页 | 37 / 7 — Single Phase, Isolated, Power Monitoring IC. ACS71020 with Voltage Zero … |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
Single Phase, Isolated, Power Monitoring IC. ACS71020 with Voltage Zero Crossing and Overcurrent Detection
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Single Phase, Isolated, Power Monitoring IC ACS71020 with Voltage Zero Crossing and Overcurrent Detection xKMATR-I2C OPERATING CHARACTERISTICS:
Valid through the full range of TA, VCC = VCC(nom), REXT = 10 kΩ, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit I2C INTERFACE CHARACTERISTICS [1]
Bus Free Time Between Stop and Start tBUF 1.3 – – µs Hold Time Start Condition thdSTA 0.6 – – µs Setup Time for Repeated Start Condition tsuSTA 0.6 – – µs SCL Low Time tLOW 1.3 – – µs SCL High Time tHIGH 0.6 – – µs Data Setup Time tsuDAT 100 – – µs Data Hold Time thdDAT 0 – 900 µs Setup Time for Stop Condition tsuSTO 0.6 – – µs Logic Input Low Level (SDA, SCL pins) VIL – – 30 %VCC Logic Input High Level (SDA, SCL pins) VIH 70 – – %VCC Logic Input Current IIN Input voltage on SDA or SCL = 0 V to VCC –1 – 1 µA Output Low Voltage (SDA) VOL SDA sinking = 1.5 mA – – 0.36 V Clock Frequency (SCL pin) fCLK – – 400 kHz Output Fall Time (SDA pin) tf REXT = 2.4 kΩ, CB = 100 pF – – 250 ns I2C Pull-Up Resistance REXT 2.4 10 – kΩ Total Capacitive Load for Each of SDA and SCL Buses CB – – 20 pF [1] These values are ratiometric to the supply voltage, I2C Interface Characteristics are ensured by design and not factory tested. t t t t t t suSTA hdSTA suDAT hdDAT suSTO BUF SDA SCL t t LOW HIGH
Figure 2: I2C Interface Timing
Allegro MicroSystems, LLC 7 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Selection Guide Absolute Maximum Ratings Isolation Characteristics Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Digital I/O Electrical Characteristics Data Acquisition ADCs Raw Signal Sensitivity and Offset Trim Phase Compensation Zero Crossing Power Calculations Digital Communication Registers and EEPROM EEPROM Error Checking and Correction (ECC) Memory Map Volatile Memory Map Application Connections Recommended PCB Layout Package Outline Drawing
Valid through the full range of TA, VCC = VCC(nom), REXT = 10 kΩ, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit I2C INTERFACE CHARACTERISTICS [1]
Bus Free Time Between Stop and Start tBUF 1.3 – – µs Hold Time Start Condition thdSTA 0.6 – – µs Setup Time for Repeated Start Condition tsuSTA 0.6 – – µs SCL Low Time tLOW 1.3 – – µs SCL High Time tHIGH 0.6 – – µs Data Setup Time tsuDAT 100 – – µs Data Hold Time thdDAT 0 – 900 µs Setup Time for Stop Condition tsuSTO 0.6 – – µs Logic Input Low Level (SDA, SCL pins) VIL – – 30 %VCC Logic Input High Level (SDA, SCL pins) VIH 70 – – %VCC Logic Input Current IIN Input voltage on SDA or SCL = 0 V to VCC –1 – 1 µA Output Low Voltage (SDA) VOL SDA sinking = 1.5 mA – – 0.36 V Clock Frequency (SCL pin) fCLK – – 400 kHz Output Fall Time (SDA pin) tf REXT = 2.4 kΩ, CB = 100 pF – – 250 ns I2C Pull-Up Resistance REXT 2.4 10 – kΩ Total Capacitive Load for Each of SDA and SCL Buses CB – – 20 pF [1] These values are ratiometric to the supply voltage, I2C Interface Characteristics are ensured by design and not factory tested. t t t t t t suSTA hdSTA suDAT hdDAT suSTO BUF SDA SCL t t LOW HIGH
Figure 2: I2C Interface Timing
Allegro MicroSystems, LLC 7 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Selection Guide Absolute Maximum Ratings Isolation Characteristics Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Digital I/O Electrical Characteristics Data Acquisition ADCs Raw Signal Sensitivity and Offset Trim Phase Compensation Zero Crossing Power Calculations Digital Communication Registers and EEPROM EEPROM Error Checking and Correction (ECC) Memory Map Volatile Memory Map Application Connections Recommended PCB Layout Package Outline Drawing