Datasheet ADSP-SC570, ADSP-SC571, ADSP-SC572, ADSP-SC573, ADSP-21571, ADSP-21573 (Analog Devices) - 8

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ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573
The system configuration is flexible, but a typical configuration is 512 Kb DM, 128 Kb PM, and 128 Kb of instruction cache,
0x FFFF FFFF RESERVED
with the remaining L1 memory configured as SRAM. Each
0x C000 0000 DMC0 (1GB)
addressable memory space outside the L1 memory can be
0x 8000 0000
accessed either directly or via cache.
SPI2 FLASH (512MB) 0x 6000 0000
The memory map in Table 4 gives the L1 memory address space
0x 5000 0000
and shows multiple L1 memory blocks offering a configurable
0x 4C00 0000
mix of SRAM and cache.
RESERVED 0x 4800 0000 L1 Master and Slave Ports 0x 4400 0000
Each SHARC+ core has two master ports and two slave ports to
0x 4000 0000 SYSTEM MMR
and from the system fabric. One master port fetches instruc-
0x 3000 0000 RESERVED
tions. The second master port drives data to the system world.
0x 28B8 FFFF SHARC2 L1 MULTI-MEMORY SPACE
Slave port 1 together with slave port 2 (MDMA) run conflict
0x 28A4 0000
free access to the individual memory blocks. For the slave port
RESERVED 0x 2838 FFFF
address, refer to the L1 memory address map in Table 4.
SHARC1 L1 MULTI-MEMORY SPACE 0x 2824 0000 UNIFIED RESERVED BYTE ADDRESS L1 On-Chip Memory Bandwidth 0x 202B FFFF SPACE
The internal memory architecture allows programs to have four
0x 2028 0000 RESERVED
accesses at the same time to any of the four blocks, assuming no
0x 2011 7FFF L2 BOOT ROM 2 (0.25Mb)
block conflicts. The total bandwidth is realized using both the
(SHARC® CORES) 0x 2824 0000
DMD and PMD buses (2 × 64-bits CCLK speed and 2 × 32-bit
0x 201B FFFF
SYSCLK speed).
RESERVED 0x 2018 0000 Instruction and Data Cache 0x 2010 FFFF L2 BOOT ROM 1 (0.25Mb) (SHARC® CORES)
The ADSP-SC57x/ADSP-2157x processors also include a
0x 2010 8000
traditional instruction cache (I-cache) and two data caches
0x 2011 8000 L2 BOOT ROM 2 (0.25Mb)
(D-cache) (PM/DM caches) with parity support for all caches.
(SHARC® CORES) 0x 2011 0000 L2 BOOT ROM 1 (0.25Mb)
These caches support one instruction access and two data
(SHARC® CORES) 0x 2010 8000
accesses over the DM and PM buses, per CCLK cycle. The cache
L2 BOOT ROM 0 (0.25Mb) (ARM® CORE 0) 0x 2010 0000
controllers automatically manage the configured L1 memory.
L2 SRAM (8Mb)
The system can configure part of the L1 memory for automatic
0x 2000 0000 0x 2000 0000 RESERVED
management by the cache controllers. The sizes of these caches
0x 0038 FFFF L1 BLOCK 3 SRAM (0.5Mb)
are independently configurable from 0 kB to a maximum of
0x 0038 0000
128 kB each. The memory not managed by the cache controllers
RESERVED RESERVED ADDRESS SP SHARC® PRIV 0x 0030 FFFF E C
is directly addressable by the processors. The controllers ensure
A L1 BLOCK 2 SRAM (0.5Mb) 0x 0030 0000
the data coherence between the two data caches. The caches
RESERVED ARM® 0x 002D FFFF A
provide user-controllable features such as full and partial lock-
A C T L1 BLOCK 1 SRAM (1Mb) E E ADDRESS SP
ing, range bound invalidation, and flushing.
0x 1000 1000 0x 002C 0000 ARM® L2 CONFIG REGS (4KB) RESERVED 0x 1000 0000 0x 0025 FFFF System Event Controller (SEC) Input RESERVED L1 BLOCK 0 SRAM (1Mb) 0x 0000 7FFF 0x 0024 0000 RESERVED/CORE MMRs/
The output of the system event controller (SEC) controller is
ARM® BOOT (32KB) OTHER MEMORY ALIASES 0x 0000 0000 0x 0000 0000
forwarded to the core event controller (CEC) to respond directly to all unmasked system-based interrupts. The SEC also Figure 5. ADSP-SC57x/ADSP-2157x Memory Map supports nesting including various SEC interrupt channel arbi- tration options. The processor automatically stacks the
SHARC+ CORE ARCHITECTURE
arithmetic status (ASTATx and ASTATy) registers and mode (MODE1) register in parallel with the interrupt servicing for all The ADSP-SC57x/ADSP-2157x processors are code compatible SEC channels. at the assembly level with the ADSP-2148x, ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x,
Core Memory-Mapped Registers (CMMR)
ADSP-2116x, and with the first-generation ADSP-2106x The core memory-mapped registers (CMMR) control the L1 SHARC processors. instruction and data cache, BTB, L2 cache, parity error, system The ADSP-SC57x/ADSP-2157x processors share architectural control, debug, and monitor functions. features with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-214xx, and ADSP-2116x SIMD SHARC processors, shown in Figure 4 and detailed in the following sections. Rev. B | Page 8 of 142 | June 2018 Document Outline System Features Memory Additional Features Table Of Contents Revision History General Description ARM Cortex-A5 Processor Generic Interrupt Controller (GIC), PL390 (ADSP-SC57x Only) Generic Interrupt Controller Port0 (GICPORT0) Generic Interrupt Controller Port1 (GICPORT1) L2 Cache Controller, PL310 (ADSP-SC57x Only) SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory SHARC+ Core L1 Memory in Multiprocessor Space One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features ARM TrustZone Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Parity Protected ARM L1 Cache Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Enhanced Parallel Peripheral Interface (EPPI) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Link Port (LP) ADC Control Module (ACM) Interface Ethernet Media Access Controller (EMAC) Audio Video Bridging (AVB) Support Precision Time Protocol (PTP) IEEE 1588 Support Controller Area Network (CAN) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Housekeeping Analog-to-Digital Converter (HADC) USB 2.0 On the Go (OTG) Dual-Role Device Controller (BGA Only) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts Mobile Storage Interface (MSI) System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator and USB Crystal Oscillator Clock Distribution Unit (CDU) Power-Up Clock Out/External Clock Booting Thermal Monitoring Unit (TMU) Power Supplies Power Management Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages (BSPs) for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 176-Lead LQFP Signal Descriptions GPIO Multiplexing for 176-Lead LQFP Package ADSP-SC57x/ADSP-2157x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Current from High Speed Peripheral Operation Data Transmission Current HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications TMU TMU Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing DDR3 SDRAM Clock and Control Cycle Timing DDR3 SDRAM Read Cycle Timing DDR3 SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface (EPPI) Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAI0 Pin to DAI0 Pin Direct Routing Up/Down Counter/Rotary Encoder Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) 10/100 EMAC Timing 10/100/1000 EMAC Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Mobile Storage Interface (MSI) Controller Timing Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 176-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide