Datasheet ADSP-21477, ADSP-21478, ADSP-21479 (Analog Devices) - 3

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ADSP-21477/ ADSP-21478/ ADSP-21479 GENERAL DESCRIPTION
The ADSP-2147x SHARC® processors are members of the
Table 2. ADSP-2147x Family Features (Continued)
SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, and ADSP-2116x DSPs as well as with first
-21477 -21478 -21479
generation ADSP-2106x SHARC processors in SISD (single- instruction, single-data) mode. These processors are 32-bit/
Feature ADSP ADSP ADSP
40-bit floating-point processors optimized for high perfor- Watch Dog Timer2 No Yes mance audio applications with a large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Real-Time Clock2, 3 No Yes digital applications interface (DAI). Shift Register2 No Yes Table 1 shows performance benchmarks for the ADSP-2147x IDP/PDAP Yes processors. Table 2 shows the features of the individual product offerings. UART 1 DAI (SRU)/DPI (SRU2) 20/14 Pins
Table 1. Processor Benchmarks
S/PDIF Transceiver 1
Speed Speed
SPI 2
Benchmark Algorithm (at 300 MHz) (at 200 MHz)
1024 Point Complex FFT 30.59 μs 45.885 μs TWI 1 (Radix 4, with Reversal) SRC SNR Performance –128 dB FIR Filter (per Tap)1 1.66 ns 2.49 ns Thermal Diode4 Yes IIR Filter (per Biquad)1 6.65 ns 9.975 ns VISA Support Yes Matrix Multiply (Pipelined) [3 × 3] × [3 × 1] 14.99 ns 22.485 ns 100-Lead 196-Ball CSP_BGA [4 × 4] × [4 × 1] 26.66 ns 39.99 ns LQFP 100-Lead LQFP Divide (y/×) 11.61 ns 17.41 ns 88-Lead 88-lead LFCSP_VQ Package1 LFCSP_VQ Inverse Square Root 18.08 ns 27.12 ns 1 1 Assumes two files in multichannel SIMD mode. The 100-lead and 88-lead packages of the processors do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function Descriptions.
Table 2. ADSP-2147x Family Features
2 Available on the 196-ball CSP_BGA package only. 3 Real Time Clock (RTC) is supported only for products with a temperature range of 0°C to +70°C and not supported for all other temperature grades.
7 8 9
4 Available on the 88-lead and 100-lead packages only.
-2147 -2147 -2147
The diagram on Page 1 shows the two clock domains (core and I/O processor) that make up the ADSP-2147x processors. The
Feature ADSP ADSP ADSP
core clock domain contains the following features. Frequency 200 MHz Up to 300 MHz • Two processing elements (PEx, PEy), each of which com- RAM 2M bits 3M bits 5M bits prises an ALU, multiplier, shifter, and data register file ROM N/A 4M bits • Two data address generators (DAG1, DAG2) 4 units (3 in 100-lead • A program sequencer with instruction cache Pulse-Width Modulation 3 package) • PM and DM buses capable of supporting 2 × 64-bit data External Port Interface transfers between memory and the core at every core pro- (SDRAM, AMI)1 No Yes, 16-Bit cessor cycle • One periodic interval timer with pinout Serial Ports 8 • On-chip SRAM (up to 5M bit) Direct DMA from SPORTs to External Memory No Yes • A JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user break- FIR, IIR, FFT Accelerator Yes points, which allows flexible exception handling. Automotive models MediaLB Interface No only Rev. D | Page 3 of 76 | April 2017 Document Outline SHARC Processor Summary Revision History Product Application Restriction General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth ROM Based Security Digital Transmission Content Protection Family Peripheral Architecture External Memory External Port SIMD Access to External Memory VISA and ISA Access to External Memory SDRAM Controller Asynchronous Memory Controller External Port Throughput MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Pulse-Width Modulation Timers 2-Wire Interface Port (TWI) Shift Register I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer (WDT) Real-Time Clock System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Maximum Power Dissipation Package Information ESD Sensitivity Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Shift Register Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-LFCSP_VQ Lead Assignment 100-LQFP_EP Lead Assignment 196-BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide