Datasheet ADSP-21261, ADSP-21262, ADSP-21266 (Analog Devices) - 10

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ADSP-21261/ ADSP-21262/ ADSP-21266 PIN FUNCTION DESCRIPTIONS
The ADSP-2126x pin definitions are listed below. Inputs identi- DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI and fied as synchronous (S) must meet timing requirements with AD15–0 (NOTE: These pins have internal pull-up resistors.) respect to CLKIN (or with respect to TCK for TMS, TDI). The following symbols appear in the Type column of Table 6: Inputs identified as asynchronous (A) can be asserted asynchro- A = asynchronous, G = ground, I = input, O = output, nously to CLKIN (or to TCK for TRST). Tie or pull unused P = power supply, S = synchronous, (A/D) = active drive, inputs to VDDEXT or GND, except for the following: (O/D) = open-drain, and T = three-state.
Table 6. Pin Descriptions State During and Pin Type After Reset Function
AD15–0 I/O/T Rev. 0.1 silicon—
Parallel Port Address/Data.
The parallel port and its corresponding DMA unit output AD15–0 pins are addresses and data for peripherals on these multiplexed pins. The multiplex state is deter- driven low both mined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each during and after AD pin has a 22.5 k internal pull-up resistor. See Address Data Modes on Page 13 for reset. details of the AD pin operation. Rev. 0.2 silicon— For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16 AD15–0 pins are external address bits, A23–8; ALE is used in conjunction with an external latch to retain three-stated and the values of the A23–8. pulled high both For 16-bit mode: ALE is automatically asserted whenever a change occurs in the address during and after bits, A15–0; ALE is used in conjunction with an external latch to retain the values of the reset. A15–0. To use these pins as flags (FLAG15–0), set (= 1) Bit 20 of the SYSCTL register and disable the parallel port. See Table 7 on Page 13 for a list of how the AD15–0 pins map to the flag pins. When configured in the IDP_PDAP_CTL register, the IDP Channel 0 can use these pins for parallel input data. RD O Output only, driven
Parallel Port Read Enable.
RD is asserted low whenever the DSP reads 8-bit or high1 16-bit data from an external memory device. When AD15–0 are flags, this pin remains deasserted. WR O Output only, driven
Parallel Port Write Enable.
WR is asserted low whenever the DSP writes 8-bit or 16-bit high1 data to an external memory device. When AD15–0 are flags, this pin remains deasserted. ALE O Output only, driven
Parallel Port Address Latch Enable.
ALE is asserted whenever the DSP drives a new low1 address on the parallel port address pin. On reset, ALE is active high. However, it can be reconfigured using software to be active low. When AD15–0 are flags, this pin remains deasserted. FLAG3–0 I/O/A Three-state
Flag Pins.
Each FLAG pin is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. These pins can be used as an SPI interface slave select output during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When Bit 16 is set (= 1) in the SYSCTL register, FLAG0 is configured as IRQ0. When Bit 17 is set (= 1) in the SYSCTL register, FLAG1 is configured as IRQ1. When Bit 18 is set (= 1) in the SYSCTL register, FLAG2 is configured as IRQ2. When Bit 19 is set (= 1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which indicates that the system timer has expired. DAI_P20–1 I/O/T Three-state with
Digital Application Interface Pins
. These pins provide the physical interface to the SRU. programmable The SRU configuration registers define the combination of on-chip peripheral inputs or pull-up outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in the SRU can be routed to any of these pins. The SRU provides the connection from the serial ports, input data port, precision clock generators, and timers to the DAI_P20–1 pins. These pins have internal 22.5 k pull-up resistors which are enabled on reset. These pull-ups can be disabled in the DAI_PIN_PULLUP register. Rev. G | Page 10 of 48 | December 2012 Document Outline Summary Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Memory and I/O Interface Features Dual-Ported On-Chip Memory DMA Controller Digital Application Interface (DAI) Serial Ports Serial Peripheral (Compatible) Interface Parallel Port Timers ROM-Based Security Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Address Data Pins as Flags Boot Modes Core Instruction Rate to CLKIN Ratio Modes Address Data Modes Product Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin-to-Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) SPI Interface Protocol—Master SPI Interface Protocol—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Environmental Conditions Thermal Characteristics 144-Lead LQFP Pin Configurations 136-Ball BGA Pin Configurations Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide