Datasheet ACT81460 (Active-Semi) - 10

ACT81460 Rev 1.0, 18-Dec-2018
VSYS OV Deglitch Time 160 200 240 µs All regulators enabled but no load, boost regulator Operating Supply Current is disabled. Charger off, power supplied from 6 8 µA VSYS. LDO1 enabled but no load. BUCK1/2, Buck-boost, Boost, and Charger disabled. Battery FET enabled Operating Supply Current 2.1 2.6 µA and supplied from VBAT. References and moni- tors enabled. LDO1 and one BUCK regulator enabled with no Operating Supply Current load. Charger disabled. Power supplied from 2.7 3.2 µA VSYS. References and monitors enabled. Thermal Low Power Threshold 70 °C Thermal Warning Temperature Temperature rising. 115 125 135 °C Thermal Shutdown Temperature Temperature rising. 140 155 170 °C Thermal Shutdown Hysteresis 25 °C Time from VSYS > UVLO threshold to Internal Power Up Delay after initial VSYS 5 ms Power-On Clear (POR) Time from VSYS > UVLO threshold to start of first Startup Delay after initial VSYS 10 ms regulator turning On. Time from I2C command to clear sleep mode to Transition time from Sleep State time when the first regulator turns ON with mini- 90 µs (SLEEP) to Active State mum turn on delay configuration. Time from turn off event to when the first power Turn Off Delay rail turns off with minimum turn off delay configura- 56 µs tion. Regulator Startup Delay Program- ONDLY=000 0 mable Range between turn on ONDLY=001 0.5 events. ONDLY=010 1 ONDLY=011 2 ms ONDLY=100 5 ONDLY=101 10 ONDLY=110 15 ONDLY=111 20 Regulator Turn Off Delay Program- Configurable in 4ms steps mable Range 0 60 ms nRESET, Delay Timing Configurable to 20, 40, 60 or 100ms. 20 100 ms
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