Datasheet ADL5531 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 20 MHz TO 500 MHz IF Gain Block |
| 页数 / 页 | 12 / 9 — Data Sheet. ADL5531. BASIC CONNECTIONS. 2.03mm. 5mm. 85mm. 78mm. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 511 Kb |
| 文件语言 | 英语 |
Data Sheet. ADL5531. BASIC CONNECTIONS. 2.03mm. 5mm. 85mm. 78mm. SOLDERING INFORMATION AND RECOMMENDED. PCB LAND PATTERN. 1.53mm. 0.71mm
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Data Sheet ADL5531 BASIC CONNECTIONS
The basic connections for operating the ADL5531 are shown
2.03mm
in Figure 16. The input and output are ac-coupled with 10 nF
1 8
(0402) capacitors. DC bias is provided to the amplifier via an inductor (Coilcraft 1008CS-471XJLC or equivalent) connected to the RFOUT pin. The bias voltage should be decoupled using
5mm 85mm 78mm
10 nF and 1 μF capacitors.
0. 1. 1. SOLDERING INFORMATION AND RECOMMENDED 4 5 PCB LAND PATTERN 1.53mm
015 Figure 15 shows the recommended land pattern for ADL5531.
0.71mm
06833- To minimize thermal impedance, the exposed pad on the Figure 15. Recommended Land Pattern package underside is soldered down to a ground plane. If multiple ground layers exist, they are stitched together using vias (a minimum of five vias is recommended). Pin 1, Pin 3, Pin 4, Pin 6, and Pin 8 can be left unconnected or can be connected to ground. Connecting these pins to ground slightly enhances thermal impedance. For more information on land pattern design and layout, refer to AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
VPOS (TESTLOOP RED) L1 C5 C6 470nH 10nF 1µF W1 GND (TESTLOOP BLACK) ADL5531 1 NC NC 8 RFIN RFOUT C1 C2 2 RFIN RFOUT 7 10nF 10nF 3 NC NC 6 4 NC CLIN 5 C3 1nF
014
NC = NO CONNECT
06833- Figure 16. Basic Connections Rev. C | Page 9 of 12 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TYPICAL SCATTERING PARAMETERS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS BASIC CONNECTIONS SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADL5531 BASIC CONNECTIONS
The basic connections for operating the ADL5531 are shown
2.03mm
in Figure 16. The input and output are ac-coupled with 10 nF
1 8
(0402) capacitors. DC bias is provided to the amplifier via an inductor (Coilcraft 1008CS-471XJLC or equivalent) connected to the RFOUT pin. The bias voltage should be decoupled using
5mm 85mm 78mm
10 nF and 1 μF capacitors.
0. 1. 1. SOLDERING INFORMATION AND RECOMMENDED 4 5 PCB LAND PATTERN 1.53mm
015 Figure 15 shows the recommended land pattern for ADL5531.
0.71mm
06833- To minimize thermal impedance, the exposed pad on the Figure 15. Recommended Land Pattern package underside is soldered down to a ground plane. If multiple ground layers exist, they are stitched together using vias (a minimum of five vias is recommended). Pin 1, Pin 3, Pin 4, Pin 6, and Pin 8 can be left unconnected or can be connected to ground. Connecting these pins to ground slightly enhances thermal impedance. For more information on land pattern design and layout, refer to AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
VPOS (TESTLOOP RED) L1 C5 C6 470nH 10nF 1µF W1 GND (TESTLOOP BLACK) ADL5531 1 NC NC 8 RFIN RFOUT C1 C2 2 RFIN RFOUT 7 10nF 10nF 3 NC NC 6 4 NC CLIN 5 C3 1nF
014
NC = NO CONNECT
06833- Figure 16. Basic Connections Rev. C | Page 9 of 12 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TYPICAL SCATTERING PARAMETERS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS BASIC CONNECTIONS SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE