Datasheet TMC6200 (TRINAMIC) - 5
| 制造商 | TRINAMIC |
| 描述 | High-power gate driver for PMSM servo or BLDC motors |
| 页数 / 页 | 47 / 5 — +VM. +VIO. 5VOUT. Figure 1.2 Standalone application using single shunt … |
| 文件格式/大小 | PDF / 1.6 Mb |
| 文件语言 | 英语 |
+VM. +VIO. 5VOUT. Figure 1.2 Standalone application using single shunt current sensing. Figure 1.3 SPI mode configuration
该数据表的模型线
文件文字版本
TMC6200 DATASHEET (Rev. 1.03 / 2019-FEB-13) 5
+VM
22n 100n O 100V I P 16V 100n
+V
P P C
M
C C V VS CE 470n VSA I T VCP Gate Voltage 12VOUT Charge Pump 12VOUT CU CB 100n Regulator 4.7µ HSU HS 5VOUT 5V Regulator VOFS U 2.2µ
+VIO
3.3V or 5V IW + USENSE I/O voltage VCC_IO LSU 100n LS OTP memory I T VCP CLK_IN 3 Phase 24MHz Oscillator CV CB 12VOUT Motor UH pd B.Dwersteg, © HSV TRINAMIC 2014 UL pd HS Chopper Control VOFS V dual line LS+HS, VH pd 6200 Break before N IV or single line VL pd Make logic S + VSENSE (HS=polarity, LS=enable) WH pd LSV LS WL pd TMC I T VCP Diagnostics FAULT CW CB 12VOUT Diagnostic Output (Short circuit,
5VOUT
Temperature) HSW SF HS OV CSN / IDRV0 W 500k Driver Strength [IDRV1 IDRV0]: 00: 0.5A 01: 0.5/1A, 10: 1A, 11: 1.5A SCK / IDRV1 Configuration + WSENSE SDI / AMPLx10 unused interface SDO / SINGLE 250k 0: xH/xL individual gate control LSW IU IV LS 1: xH=Polarity, xL=Enable control 5VOUT 1 0 pd Current Sense E
+V
N
IO
P S E A W S _ RU RV R AD D RS V OF U U V U N R C C P C E G D I D R1 R2 Use LMV641 or similar Amplification=1+R2/R1 Enable
Figure 1.2 Standalone application using single shunt current sensing +VM
22n 100n O 100V I P 16V 100n
+V
P P C
M
C C V VS CE 470n VSA I T VCP Gate Voltage 12VOUT Charge Pump 12VOUT CU CB 100n Regulator 4.7µ HSU HS 5VOUT 5V Regulator VOFS U 2.2µ
+VIO
3.3V or 5V IW + USENSE I/O voltage VCC_IO RS RP LSU 100n LS OTP memory I T VCP CLK_IN 3 Phase 24MHz Oscillator 12VOUT CV CB Motor UH pd B.Dwersteg, © HSV TRINAMIC 2014 UL pd HS Chopper Control VOFS V dual line LS+HS, VH pd Break before N IV or single line VL pd Make logic S + VSENSE RS (HS=polarity, LS=enable) WH R pd P LSV LS WL pd TMC6200 I T VCP Diagnostics FAULT 12VOUT CW CB (Short circuit,
5VOUT
Temperature) HSW SF HS OV CSN / IDRV0 W 500k SCK / IDRV1 + WSENSE RS SPI SDI / AMPLx10 SPI interface RP SDO / SINGLE 250k LSW IU IV LS pd E N S U V P E A W S _ R R R AD D V OF U U V U N R C C P C E G D I D
+VIO
Enable Current Sense
Figure 1.3 SPI mode configuration
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+VM
22n 100n O 100V I P 16V 100n
+V
P P C
M
C C V VS CE 470n VSA I T VCP Gate Voltage 12VOUT Charge Pump 12VOUT CU CB 100n Regulator 4.7µ HSU HS 5VOUT 5V Regulator VOFS U 2.2µ
+VIO
3.3V or 5V IW + USENSE I/O voltage VCC_IO LSU 100n LS OTP memory I T VCP CLK_IN 3 Phase 24MHz Oscillator CV CB 12VOUT Motor UH pd B.Dwersteg, © HSV TRINAMIC 2014 UL pd HS Chopper Control VOFS V dual line LS+HS, VH pd 6200 Break before N IV or single line VL pd Make logic S + VSENSE (HS=polarity, LS=enable) WH pd LSV LS WL pd TMC I T VCP Diagnostics FAULT CW CB 12VOUT Diagnostic Output (Short circuit,
5VOUT
Temperature) HSW SF HS OV CSN / IDRV0 W 500k Driver Strength [IDRV1 IDRV0]: 00: 0.5A 01: 0.5/1A, 10: 1A, 11: 1.5A SCK / IDRV1 Configuration + WSENSE SDI / AMPLx10 unused interface SDO / SINGLE 250k 0: xH/xL individual gate control LSW IU IV LS 1: xH=Polarity, xL=Enable control 5VOUT 1 0 pd Current Sense E
+V
N
IO
P S E A W S _ RU RV R AD D RS V OF U U V U N R C C P C E G D I D R1 R2 Use LMV641 or similar Amplification=1+R2/R1 Enable
Figure 1.2 Standalone application using single shunt current sensing +VM
22n 100n O 100V I P 16V 100n
+V
P P C
M
C C V VS CE 470n VSA I T VCP Gate Voltage 12VOUT Charge Pump 12VOUT CU CB 100n Regulator 4.7µ HSU HS 5VOUT 5V Regulator VOFS U 2.2µ
+VIO
3.3V or 5V IW + USENSE I/O voltage VCC_IO RS RP LSU 100n LS OTP memory I T VCP CLK_IN 3 Phase 24MHz Oscillator 12VOUT CV CB Motor UH pd B.Dwersteg, © HSV TRINAMIC 2014 UL pd HS Chopper Control VOFS V dual line LS+HS, VH pd Break before N IV or single line VL pd Make logic S + VSENSE RS (HS=polarity, LS=enable) WH R pd P LSV LS WL pd TMC6200 I T VCP Diagnostics FAULT 12VOUT CW CB (Short circuit,
5VOUT
Temperature) HSW SF HS OV CSN / IDRV0 W 500k SCK / IDRV1 + WSENSE RS SPI SDI / AMPLx10 SPI interface RP SDO / SINGLE 250k LSW IU IV LS pd E N S U V P E A W S _ R R R AD D V OF U U V U N R C C P C E G D I D
+VIO
Enable Current Sense
Figure 1.3 SPI mode configuration
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