Datasheet A80601, A80601-1 (Allegro) - 7

A80601 and High Power LED Driver with Pre-Emptive Boost A80601-1 for Ultra-High Dimming Ratio and Low Output Ripple ELECTRICAL CHARACTERISTICS [1] (continued): Unless otherwise noted, specifications are valid at VIN = 12 V, TJ = 25°C, • indi- cates specifications guaranteed over the full operating temperature range with TJ = –40°C to 125°C, typical specifications are at TJ = 25°C Characteristics Symbol Test Conditions Min. Typ. Max. Unit OVERVOLTAGE PROTECTION
OVP Pin Voltage Threshold VOVP(th) OVP pin connected to VOUT ● 2.2 2.5 2.8 V Current into OVP pin at 125ºC 140 146.5 153 µA OVP Pin Sense Current Threshold iOVP(th) Measured over temperature ● 140 150 160 µA OVP Sense Current Temperature Coefficient [2] ∆iOVP Current into OVP pin − −36 − nA/ºC OVP Pin Leakage Current IOVPLKG VOUT = 16 V, EN = L ● − 0.1 1 µA − − 4 % OVP Variation at Output ΔOVP Measured at VOUT when ROVP = 188 kΩ ● − − 7 % Measured at V Undervoltage Detection Threshold V OUT when ROVP = 188 kΩ [2] 2.4 2.55 2.7 V UVP(th) Measured at VOUT when ROVP = 0 Ω 0.13 0.20 0.25 V
BOOST SWITCH GATE DRIVER
Gate Driver Supply Voltage VDRV Measured at VIN > 7.5 V − 6.5 − V Gate Driver Pull-Up and Pull-Down RGDRV Measured at iGDRV = 100 mA − 2.5 − Ω Gate Pull-Down When Disabled RGDRV_OFF EN = L, VIN = 0 V − 100 − kΩ Peak Sink Current [2] iSINK Measured at VGDRV = VDRV − 2 − A Peak Source Current [2] iSOURCE Measured at VGDRV = 0 V − 2 − A Gate Rise / Fall Time [2] t Measured with CLOAD = 1.5 nF; RISE, tFALL V − 7 − ns GDRV between 10% and 90% of VDRV Minimum Gate Driver On-Time tSW(ON) ● − − 100 ns Minimum Gate Driver Off-Time tSW(OFF) ● − − 100 ns
BOOST SWITCH CURRENT SENSE
Primary Current Sense Limit i Exceeding iCS(LIM1) causes gate driver to CS(LIM1) truncate existing cycle, but does not shut down ● 175 210 245 mV Secondary Current Sense Limit i Exceeding iCS(LIM2) causes gate driver to shut CS(LIM2) down and latch off − 300 − mV Secondary Current Sense Limit Overdrive CS threshold by 10%, excluding Propagation delay [2] tCSDELAY leading edge blanking − 32 − ns
OSCILLATOR FREQUENCY
R Oscillator Frequency f FSET = 10 kΩ ● 1.95 2.15 2.35 MHz SW RFSET = 110 kΩ − 200 − kHz FSET Pin Voltage VFSET RFSET = 10 kΩ − 1.00 − V
SYNCHRONIZATION
V Sync Input Logic Level SYNCL FSET/SYNC pin logic Low ● − − 0.4 V VSYNCH FSET/SYNC pin logic High ● 1.5 − − V Synchronized PWM Frequency fSWSYNC ● 260 − 2300 kHz Synchronization Input Min Off-Time tPWSYNCOFF ● 150 − − ns Synchronization Input Min On-Time tPWSYNCON ● 150 − − ns Continued on the next page… Allegro MicroSystems, LLC 7 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Applications Package Selection Guide Absolute Maximum Ratings Thermal Characteristics Typical Application – SEPIC Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Functional Description Enabling the IC Powering Up: LED Detection Phase Powering Up: Boost Output Undervoltage Soft Start Function Frequency Selection Synchronization Loss of External Sync Signal Switching Frequency Dithering Clock Out Function LED Current Setting PWM Dimming Pre-Emptive Boost (PEB) Analog Dimming ADIM Mode APWM Mode Extending LED Dimming Ratio Analog Dimming with External Voltage VDD VDRV Shutdown Fault Detection and Protection FAULT Status LED String Partial-Short Detect Overvoltage Protection Boost Switch Overcurrent Protection Input Overcurrent Protection and Disconnect Switch Setting the Input Current Sense Resistor Input UVLO Fault Protection During Operation Package Outline Drawing Appendix: External MOSFET Selection Guide