Datasheet MAX1661, MAX1662, MAX1663 (Maxim) - 3

Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface MAX1661/MAX1662/MAX1663 ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are for TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Measured from 90% of the SMBCLK rising Start-Condition Setup Time tSU:STA 4.7 µs edge to 90% of the SMBDATA falling edge Measured from 10% of the falling edge Start-Condition Hold Time tHD:STA of SMBDATA to 90% of the falling edge of 4 µs SMBCLK Measured from 90% of the rising edge SMBus Stop-Condition Setup tSU:STO of SMBCLK to 10% of the rising edge of 4 µs Time SMBDATA VCC = 4.5V SMBDATA Valid to SMBCLK 10% or 90% of SMBDATA 500 to 5.5V Rising Edge Time, Slave tSU:DAT to 10% of the rising edge ns Clocking in Data of SMBCLK VCC = 2.7V 1000 to 4.5V SMBCLK Falling Edge to tHD:DAT (Notes 4, 5) 0 µs SMBDATA Transition Hold Time SMBCLK Falling Edge to Tested with a 10kΩ pull-up resistor on tDV 1 µs SMBus Data Valid Time SMBDATA (Note 6) SMBus Bus-Free Time tBUF Between stop and start conditions (Note 7) 4.7 µs SMBus Write to I/O_ Measured from SMBCLK rising edge to 10% tP:I/O 100 ns Propagation Delay or 90% of I/O (Note 4) I/O Data Valid to SMBCLK Measured from 10% or 90% of VI/O to 10% of tSU:I/O 15 µs Rising-Edge Setup Time the rising edge of SMBCLK (Note 8) I/O Data Hold Time tHD:I/O (Note 8) 0 µs Measured from the 10% point of the falling START-STOP Software-Interrupt tLOW:SS edge of SMBDATA to the 10% point of the 10 15 30 µs Pulse Width rising edge of SMBDATA (Note 7)
Note 1:
Specifications from 0°C to -40°C are guaranteed by design, not production tested.
Note 2:
Supply current is specified for static state only.
Note 3:
The SMBus logic block is a static design that works with clock frequencies down to DC. While slow operation is possible, it violates the 10kHz minimum clock frequency of the SMBus specifications, and may monopolize the bus.
Note 4:
Refer to Figures 2a and 2b for SMBus timing parameter definitions (write and read diagrams).
Note 5:
A transition must internally provide a hold time of 300ns to accommodate for the undefined region of the falling edge.
Note 6:
Refer to Figure 3 for the acknowledge timing diagram and tDV parameter definition.
Note 7:
Refer to Figure 5 for START-STOP interrupt timing diagrams and parameter definitions.
Note 8:
Refer to Figure 4 for I/O setup and hold timing parameter definitions.
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