Datasheet MAX1661, MAX1662, MAX1663 (Maxim) - 10

Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface
SLAVE ACKNOWLEDGE START STOP (ACK) SMBCLK tLOW:SS SMBDATA tBUF DATA LINE HELD DUMMY BIT (1) LOW BY SLAVE ALERT START-STOP INTERRUPT ALERT RESPONSE ADDRESS ACTUAL SLAVE ADDRESS (0001100) (0100000 IN THIS EXAMPLE) Figure 5. START-STOP Software Interrupt Timing Diagram and Alert Response
START-STOP Software Interrupt
monly used in power-switching applications. Other fac- The START-STOP interrupt is a method for the slave tors include the VGS, the input capacitance of the MOS- device to initiate a signal over the 2-wire interface with- FET, and the pull-up resistor value used in the circuit. out the need for a third (interrupt) wire. A START-STOP Typical MOSFET gate capacitance ranges from 150pF interrupt is a start condition followed by a stop condi- to 2000pF. Increasing the RC time constant slows down tion; in other words, SMBDATA goes low and then high the MOSFET’s response, but provides for a smoother with SMBCLK high (Figure 5 shows the START-STOP transition. interrupt and a subsequent Alert Response transmis- sion used to clear the interrupt). The START-STOP
Power-On Reset
function can be disabled (masked) by setting the data The power-on reset circuit keeps the external MOSFETs register mask SS (bit 6) high. off during a power-up sequence. When the supply volt-
MAX1661/MAX1662/MAX1663
age falls below the power-on reset threshold voltage, In order to avoid bus collisions, the START-STOP inter- the MAX1662/MAX1663’s outputs reset to a high- rupt will not occur when the bus is busy. If the device impedance state, and the MAX1661’s outputs reset to a begins a start condition simultaneously with another low state. During the initial power-up sequence, as VCC transmitter on the bus, it recognizes the falling SMB- increases, the ALERT pin goes low and then high, CLK as a collision and re-transmits the interrupt when which indicates the device is powered on. The time the bus becomes available. Upon thermal shutdown or between the low and high state on ALERT is the power- a transition on an I/O line, the device issues only one on delay time. Below VCC = 0.8V (typical) the POR START-STOP interrupt, and won’t repeat it unless there states can’t be enforced, and the I/O pins of all ver- has been a collision. However, thermal-shutdown faults, sions exhibit increasingly weak pull-down current capa- not being edge triggered, may result in a continuous bility, eventually becoming high impedance. stream of START-STOP bits.
Thermal Shutdown Input/Output Pins
These devices have internal thermal-shutdown circuitry Each input/output (I/O) is protected by an internal that turns off all output stages (I/O pins) when the junc- 20mA (typical) current-limit circuit. The I/O current limit tion temperature exceeds +140°C typical. Thermal depends on the supply voltage and the voltage applied shutdown only occurs during an overload condition on to the I/O pins (see Typical Operating Characteristics). the I/O pins. The device cycles between thermal shut- The typical I/O bias current is 0.5µA to VI/O_ = 28V. down and the overcurrent condition until the overload The ability of the I/Os to sink current depends on VCC condition is removed. This could cause a sustained as well as the voltage on the I/O. Typical pull-down on- START-STOP interrupt and, in the extreme case, tie up resistance at VCC = 2.7V and 5.5V is 106Ω and 66Ω, the master controller. However, the device asserts respectively. I/O source and sink capability can affect ALERT low, indicating this fault status. the rise and fall times of external power MOSFETs com-
10 ______________________________________________________________________________________