Datasheet MAX1661, MAX1662, MAX1663 (Maxim) - 9
| 制造商 | Maxim |
| 描述 | Serial to Parallel Parallel to Serial Converters and Load Switch Controllers with SMBus Interface |
| 页数 / 页 | 16 / 9 — Serial-to-Parallel/Parallel-to-Serial Converters and. Load-Switch … |
| 文件格式/大小 | PDF / 152 Kb |
| 文件语言 | 英语 |
Serial-to-Parallel/Parallel-to-Serial Converters and. Load-Switch Controllers with SMBus Interface. MAX1661/MAX1662/MAX1663
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Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface MAX1661/MAX1662/MAX1663
R/W BIT ACKNOWLEDGE BIT MOST SIGNIFICANT CLOCKED CLOCKED BIT OF DATA INTO SLAVE INTO MASTER CLOCKED INTO MASTER SMBCLK • • • SLAVE PULLING SMBDATA LOW SMBDATA • • • tDV tDV Figure 3. SMB Serial-Interface Timing—Acknowledge and Data Valid SLAVE ACKNOWLEDGE SLAVE ADDRESS ADDRESS ACKNOWLEDGE MSB LSB I/O (ACK) LATCHED DATA START R/W BIT MSB DATA LSB SMBCLK tSU:I/O tHD:I/O (NOTE 1) (NOTE 1) SMBDATA THSD DATA3 DATA2 DATA1 SLAVE PULLS 4 ZEROS (NOT USED) SMBDATA LOW
NOTE 1:
THE SETUP AND HOLD TIMING LIMITS ARE ABSOLUTE LIMITS (15µs MIN AND 0µs MIN, RESPECTIVELY) AND DO NOT NECESSARILY CORRESPOND TO A PARTICULAR CLOCK EDGE. Figure 4. I/O Read Timing Diagram rupt, the host (Bus Master) interrogates the bus slave
Clearing Interrupts via Alert Response
devices via a special receive-byte operation that When a fault occurs, ALERT asserts and latches low. If includes the alert response address. The data returned the fault is momentary and disappears before the by this receive-byte operation is the address of the device is serviced, ALERT remains asserted. Normally, offending slave device. The interrupt pointer address the master sends out the Alert Response address fol- can activate several different slave devices simultane- lowed by a read bit (00011001). ALERT clears when ously. If more than one slave attempts to respond, bus the device responds by successfully putting its arbitration rules apply, with the lowest address code address on the bus.
Reading the Alert Response
going first. The other device(s) will not generate an
address is the only method for clearing hardware
acknowledge and will continue to hold the ALERT line
and software interrupt latches.
Clearing the interrupt low or repeat the START-STOP interrupt until serviced. has no effect on the state of the status registers.
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R/W BIT ACKNOWLEDGE BIT MOST SIGNIFICANT CLOCKED CLOCKED BIT OF DATA INTO SLAVE INTO MASTER CLOCKED INTO MASTER SMBCLK • • • SLAVE PULLING SMBDATA LOW SMBDATA • • • tDV tDV Figure 3. SMB Serial-Interface Timing—Acknowledge and Data Valid SLAVE ACKNOWLEDGE SLAVE ADDRESS ADDRESS ACKNOWLEDGE MSB LSB I/O (ACK) LATCHED DATA START R/W BIT MSB DATA LSB SMBCLK tSU:I/O tHD:I/O (NOTE 1) (NOTE 1) SMBDATA THSD DATA3 DATA2 DATA1 SLAVE PULLS 4 ZEROS (NOT USED) SMBDATA LOW
NOTE 1:
THE SETUP AND HOLD TIMING LIMITS ARE ABSOLUTE LIMITS (15µs MIN AND 0µs MIN, RESPECTIVELY) AND DO NOT NECESSARILY CORRESPOND TO A PARTICULAR CLOCK EDGE. Figure 4. I/O Read Timing Diagram rupt, the host (Bus Master) interrogates the bus slave
Clearing Interrupts via Alert Response
devices via a special receive-byte operation that When a fault occurs, ALERT asserts and latches low. If includes the alert response address. The data returned the fault is momentary and disappears before the by this receive-byte operation is the address of the device is serviced, ALERT remains asserted. Normally, offending slave device. The interrupt pointer address the master sends out the Alert Response address fol- can activate several different slave devices simultane- lowed by a read bit (00011001). ALERT clears when ously. If more than one slave attempts to respond, bus the device responds by successfully putting its arbitration rules apply, with the lowest address code address on the bus.
Reading the Alert Response
going first. The other device(s) will not generate an
address is the only method for clearing hardware
acknowledge and will continue to hold the ALERT line
and software interrupt latches.
Clearing the interrupt low or repeat the START-STOP interrupt until serviced. has no effect on the state of the status registers.
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