Datasheet MAX1661, MAX1662, MAX1663 (Maxim) - 8

Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface
A B C D E F G H I J K tLOW tHIGH SMBCLK SMBDATA tSU:STA tHD:STA tSU:DAT tSU:STO tBUF A = START CONDITION E = SLAVE PULLS SMBDATA LINE LOW I = ACKNOWLEDGE CLOCK PULSE B = MSB OF ADDRESS CLOCKED INTO SLAVE F = ACKNOWLEDGE BIT CLOCKED INTO MASTER J = STOP CONDITION C = LSB OF ADDRESS CLOCKED INTO SLAVE G = MSB OF DATA CLOCKED INTO MASTER K = NEW START CONDITION D = R/W BIT CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO MASTER
Receive-Byte Format ADDRESS READ ACK DATA
ACK START 1 bit 1 bit 1 bit STOP 7 bits 8 bits CONDITION (high) (low) (high-Z) CONDITION ACK = SMBDATA High Shaded = Slave Transmission Figure 2b. SMBus Receive-Byte Timing Diagram and Format
MAX1661/MAX1662/MAX1663 Table 3. Format for Receive-Byte Data BIT NAME POR STATE FUNCTION LATCHED
7 (MSB) — 0 Not used — 6 — 0 Not used — 5 — 0 Not used — 4 — 0 Not used — 3 THSD N/A This bit indicates a thermal shutdown. Yes 2 Data 3 N/A This bit indicates the state of I/O3 (high or low). No 1 Data 2 N/A This bit indicates the state of I/O2 (high or low). No 0 Data 1 N/A This bit indicates the state of I/O1 (high or low). No and with the software START-STOP method (software The MAX1661/MAX1662/MAX1663 are slave-only interrupts are discussed in the START-STOP Software devices that never initiate communications, except Interrupt section). The I/O interrupts can be masked when asserting an interrupt by forcing ALERT low, or individually. In addition, the software START-STOP via the software START-STOP interrupt. interrupt can be masked independently. The power-on- reset state masks the START-STOP interrupt, as well as
Alert Response Address (0001100)
the individual I/O interrupts to the ALERT pin (Table 1). The Alert Response (interrupt pointer) address pro- The thermal-shutdown interrupt cannot be masked. vides quick fault identification for simple slave devices Note that excessive noise on the supply can cause that lack the complex, expensive logic needed to be a false interrupts (see Applications Information). bus master. When a slave device generates an inter-
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