Datasheet MAX1661, MAX1662, MAX1663 (Maxim) - 7
| 制造商 | Maxim |
| 描述 | Serial to Parallel Parallel to Serial Converters and Load Switch Controllers with SMBus Interface |
| 页数 / 页 | 16 / 7 — Serial-to-Parallel/Parallel-to-Serial Converters and. Load-Switch … |
| 文件格式/大小 | PDF / 152 Kb |
| 文件语言 | 英语 |
Serial-to-Parallel/Parallel-to-Serial Converters and. Load-Switch Controllers with SMBus Interface. MAX1661/MAX1662/MAX1663
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文件文字版本
Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface MAX1661/MAX1662/MAX1663
tP: I/O I/O A B C D E F G H I J K L M tLOW tHIGH SMBCLK SMBDATA tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF A = START CONDITION F = ACKNOWLEDGE BIT CLOCKED INTO MASTER J = ACKNOWLEDGE CLOCKED INTO MASTER B = MSB OF ADDRESS CLOCKED INTO SLAVE G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT) K = ACKNOWLEDGE CLOCK PULSE C = LSB OF ADDRESS CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO SLAVE L = STOP CONDITION, DATA EXECUTED BY SLAVE D = R/W BIT CLOCKED INTO SLAVE I = SLAVE PULLS SMBDATA LINE LOW M = NEW START CONDITION E = SLAVE PULLS SMBDATA LINE LOW
Send-Byte Format ADDRESS WRITE ACK DATA ACK
START 1 bit 1 bit 1 bit STOP 7 bits 8 bits CONDITION (low) (low) (low) CONDITION Shaded = Slave Transmission Figure 2a. SMBus Send-Byte Timing Diagram and Format
Table 2. Format for Send-Byte Data POR STATE* POR STATE* BIT NAME FUNCTION (MAX1661) (MAX1662/MAX1663)
Writes data to normal register when high; writes data to suspend 7 (MSB) SELECT N/A N/A register when low. 6 Mask SS 1 1 Masks START-STOP software interrupts when high. 5 Mask 3 1 1 Masks I/O3 interrupts when high. 4 Mask 2 1 1 Masks I/O2 interrupts when high. 3 Mask 1 1 1 Masks I/O1 interrupts when high. 2 I/O3 0 1 I/O output enable bit. I/O3 is on when this bit is low (low state). 1 I/O2 0 1 I/O output enable bit. I/O2 is on when this bit is low (low state). 0 I/O1 0 1 I/O output enable bit. I/O1 is on when this bit is low (low state). *
Note:
POR states apply to both suspend- and normal-mode registers. current I/O pin states (i.e., they are not latched). There
Interrupts
is a 15µs data-setup time requirement, due to the slow The MAX1661/MAX1662/MAX1663 generate interrupts level translators needed for high-voltage (28V) opera- (hardware and software) whenever the logic states of tion. Data-hold time is zero. the I/O pins change or when thermal shutdown occurs. Interrupts are signaled with the hardware ALERT pin
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tP: I/O I/O A B C D E F G H I J K L M tLOW tHIGH SMBCLK SMBDATA tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF A = START CONDITION F = ACKNOWLEDGE BIT CLOCKED INTO MASTER J = ACKNOWLEDGE CLOCKED INTO MASTER B = MSB OF ADDRESS CLOCKED INTO SLAVE G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT) K = ACKNOWLEDGE CLOCK PULSE C = LSB OF ADDRESS CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO SLAVE L = STOP CONDITION, DATA EXECUTED BY SLAVE D = R/W BIT CLOCKED INTO SLAVE I = SLAVE PULLS SMBDATA LINE LOW M = NEW START CONDITION E = SLAVE PULLS SMBDATA LINE LOW
Send-Byte Format ADDRESS WRITE ACK DATA ACK
START 1 bit 1 bit 1 bit STOP 7 bits 8 bits CONDITION (low) (low) (low) CONDITION Shaded = Slave Transmission Figure 2a. SMBus Send-Byte Timing Diagram and Format
Table 2. Format for Send-Byte Data POR STATE* POR STATE* BIT NAME FUNCTION (MAX1661) (MAX1662/MAX1663)
Writes data to normal register when high; writes data to suspend 7 (MSB) SELECT N/A N/A register when low. 6 Mask SS 1 1 Masks START-STOP software interrupts when high. 5 Mask 3 1 1 Masks I/O3 interrupts when high. 4 Mask 2 1 1 Masks I/O2 interrupts when high. 3 Mask 1 1 1 Masks I/O1 interrupts when high. 2 I/O3 0 1 I/O output enable bit. I/O3 is on when this bit is low (low state). 1 I/O2 0 1 I/O output enable bit. I/O2 is on when this bit is low (low state). 0 I/O1 0 1 I/O output enable bit. I/O1 is on when this bit is low (low state). *
Note:
POR states apply to both suspend- and normal-mode registers. current I/O pin states (i.e., they are not latched). There
Interrupts
is a 15µs data-setup time requirement, due to the slow The MAX1661/MAX1662/MAX1663 generate interrupts level translators needed for high-voltage (28V) opera- (hardware and software) whenever the logic states of tion. Data-hold time is zero. the I/O pins change or when thermal shutdown occurs. Interrupts are signaled with the hardware ALERT pin
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