Datasheet ADN2805 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 1.25 Gbps Clock and Data Recovery IC |
| 页数 / 页 | 16 / 4 — ADN2805. Data Sheet. OUTPUT AND TIMING SPECIFICATIONS. Table 3. Parameter … |
| 修订版 | B |
| 文件格式/大小 | PDF / 293 Kb |
| 文件语言 | 英语 |
ADN2805. Data Sheet. OUTPUT AND TIMING SPECIFICATIONS. Table 3. Parameter Conditions. Min. Typ. Max. Unit
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ADN2805 Data Sheet OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter Conditions Min Typ Max Unit
LVDS OUTPUT CHARACTERISTICS CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN Differential Output Swing VOD (see Figure 3) 240 300 400 mV Output Offset Voltage VOS (see Figure 3) 1125 1200 1275 mV Output Impedance Differential 100 Ω LVDS Outputs Timing Rise Time 20% to 80% 115 220 ps Fall Time 80% to 20% 115 220 ps Setup Time TS (see Figure 2), GbE 360 400 440 ps Hold Time TH (see Figure 2), GbE 360 400 440 ps I2C® INTERFACE DC CHARACTERISTICS LVCMOS Input High Voltage VIH 0.7 VCC V Input Low Voltage VIL 0.3 VCC V Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 μA Output Low Voltage VOL, IOL = 3.0 mA 0.4 V I2C INTERFACE TIMING See Figure 10 SCK Clock Frequency 400 kHz SCK Pulse Width High tHIGH 600 ns SCK Pulse Width Low tLOW 1300 ns Start Condition Hold Time tHD;STA 600 ns Start Condition Setup Time tSU;STA 600 ns Data Setup Time tSU;DAT 100 ns Data Hold Time tHD;DAT 300 ns SCK/SDA Rise/Fall Time tR/tF 20 + 0.1 Cb1 300 ns Stop Condition Setup Time tSU;STO 600 ns Bus Free Time Between a Stop and a Start tBUF 1300 ns REFCLK CHARACTERISTICS Optional lock-to-REFCLK mode Input Voltage Range @ REFCLKP or REFCLKN Input Low Voltage VIL 0 V Input High Voltage VIH VCC V Minimum Differential Input Drive 100 mV p-p Reference Frequency 10 160 MHz Required Accuracy 100 ppm LVTTL DC INPUT CHARACTERISTICS Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Input High Current IIH, VIN = 2.4 V 5 μA Input Low Current IIL, VIN = 0.4 V −5 μA LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage VOH, IOH = −2.0 mA 2.4 V Output Low Voltage VOL, IOL = 2.0 mA 0.4 V 1 Cb = total capacitance of one bus line in pF. If mixed with high speed mode devices, faster fall times are allowed. Rev. B | Page 4 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS JITTER SPECIFICATIONS OUTPUT AND TIMING SPECIFICATIONS Timing Characteristics ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Thermal Resistance ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION INPUT BUFFER LOCK DETECTOR OPERATION Normal Mode LOL Detector Operation Using a Reference Clock Static LOL Mode SQUELCH MODE SYSTEM RESET I2C INTERFACE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE
ADN2805 Data Sheet OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter Conditions Min Typ Max Unit
LVDS OUTPUT CHARACTERISTICS CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN Differential Output Swing VOD (see Figure 3) 240 300 400 mV Output Offset Voltage VOS (see Figure 3) 1125 1200 1275 mV Output Impedance Differential 100 Ω LVDS Outputs Timing Rise Time 20% to 80% 115 220 ps Fall Time 80% to 20% 115 220 ps Setup Time TS (see Figure 2), GbE 360 400 440 ps Hold Time TH (see Figure 2), GbE 360 400 440 ps I2C® INTERFACE DC CHARACTERISTICS LVCMOS Input High Voltage VIH 0.7 VCC V Input Low Voltage VIL 0.3 VCC V Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 μA Output Low Voltage VOL, IOL = 3.0 mA 0.4 V I2C INTERFACE TIMING See Figure 10 SCK Clock Frequency 400 kHz SCK Pulse Width High tHIGH 600 ns SCK Pulse Width Low tLOW 1300 ns Start Condition Hold Time tHD;STA 600 ns Start Condition Setup Time tSU;STA 600 ns Data Setup Time tSU;DAT 100 ns Data Hold Time tHD;DAT 300 ns SCK/SDA Rise/Fall Time tR/tF 20 + 0.1 Cb1 300 ns Stop Condition Setup Time tSU;STO 600 ns Bus Free Time Between a Stop and a Start tBUF 1300 ns REFCLK CHARACTERISTICS Optional lock-to-REFCLK mode Input Voltage Range @ REFCLKP or REFCLKN Input Low Voltage VIL 0 V Input High Voltage VIH VCC V Minimum Differential Input Drive 100 mV p-p Reference Frequency 10 160 MHz Required Accuracy 100 ppm LVTTL DC INPUT CHARACTERISTICS Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Input High Current IIH, VIN = 2.4 V 5 μA Input Low Current IIL, VIN = 0.4 V −5 μA LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage VOH, IOH = −2.0 mA 2.4 V Output Low Voltage VOL, IOL = 2.0 mA 0.4 V 1 Cb = total capacitance of one bus line in pF. If mixed with high speed mode devices, faster fall times are allowed. Rev. B | Page 4 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS JITTER SPECIFICATIONS OUTPUT AND TIMING SPECIFICATIONS Timing Characteristics ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Thermal Resistance ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION INPUT BUFFER LOCK DETECTOR OPERATION Normal Mode LOL Detector Operation Using a Reference Clock Static LOL Mode SQUELCH MODE SYSTEM RESET I2C INTERFACE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE