Datasheet AD7124-4-EP (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference |
| 页数 / 页 | 17 / 4 — AD7124-4-EP. Enhanced Product. SPECIFICATIONS. Table 1. Parameter1 Min. … |
| 文件格式/大小 | PDF / 247 Kb |
| 文件语言 | 英语 |
AD7124-4-EP. Enhanced Product. SPECIFICATIONS. Table 1. Parameter1 Min. Typ. Max. Unit. Test. Conditions/Comments
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AD7124-4-EP Enhanced Product SPECIFICATIONS
AVDD = 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V, REFINx(+) = 2.5 V, REFINx(−) = AVSS, master clock = 614.4 kHz, all specifications TMIN to TMAX, unless otherwise noted.
Table 1. Parameter1 Min Typ Max Unit Test Conditions/Comments
ADC Output Data Rate, fADC Low Power Mode 1.17 2400 SPS Mid Power Mode 2.34 4800 SPS Full Power Mode 9.38 19,200 SPS No Missing Codes2 24 Bits FS3 > 2, sinc4 filter 24 Bits FS3 > 8, sinc3 filter Resolution RMS Noise and Update Rates Integral Nonlinearity (INL) −4 ±1 +4 ppm of FSR Gain = 12 −15 ±2 +15 ppm of FSR Gain > 14 Offset Error5 Before Calibration ±15 μV Gain = 1 to 8 200/gain μV Gain = 16 to 128 After Internal Calibration/System In order of Calibration noise Offset Error Drift vs. Temperature6 Low Power Mode 10 nV/°C Gain = 1 or gain > 16 80 nV/°C Gain = 2 to 8 40 nV/°C Gain = 16 Mid Power Mode 10 nV/°C Gain = 1 or gain > 16 40 nV/°C Gain = 2 to 8 20 nV/°C Gain = 16 Full Power Mode 10 nV/°C Gain Error5, 7 Before Internal Calibration −0.0025 +0.0025 % Gain = 1, TA = 25°C −0.3 % Gain > 1 After Internal Calibration −0.016 +0.004 +0.016 % Gain = 2 to 8, TA = 25°C ±0.025 % Gain = 16 to 128 After System Calibration In order of noise Gain Error Drift vs. Temperature 1 2 ppm/°C Power Supply Rejection AIN = 1 V/gain, external reference Low Power Mode 87 dB Gain = 2 to 16 96 dB Gain = 1 or gain > 16 Mid Power Mode2 92 dB Gain = 2 to 16 100 dB Gain = 1 or gain > 16 Full Power Mode 99 dB Common-Mode Rejection8 At DC2 85 90 dB AIN = 1 V, gain = 1 105 115 dB AIN = 1 V/gain, gain 2 or 4 1029, 2 dB AIN = 1 V/gain, gain 2 or 4 115 120 dB AIN = 1 V/gain, gain ≥ 8 1059, 2 dB AIN = 1 V/gain, gain ≥ 8 Sinc3, Sinc4 Filter2 At 50 Hz, 60 Hz 120 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz At 50 Hz 120 dB 50 SPS, 50 Hz ± 1 Hz At 60 Hz 120 dB 60 SPS, 60 Hz ± 1 Hz Rev. 0 | Page 4 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
AD7124-4-EP Enhanced Product SPECIFICATIONS
AVDD = 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V, REFINx(+) = 2.5 V, REFINx(−) = AVSS, master clock = 614.4 kHz, all specifications TMIN to TMAX, unless otherwise noted.
Table 1. Parameter1 Min Typ Max Unit Test Conditions/Comments
ADC Output Data Rate, fADC Low Power Mode 1.17 2400 SPS Mid Power Mode 2.34 4800 SPS Full Power Mode 9.38 19,200 SPS No Missing Codes2 24 Bits FS3 > 2, sinc4 filter 24 Bits FS3 > 8, sinc3 filter Resolution RMS Noise and Update Rates Integral Nonlinearity (INL) −4 ±1 +4 ppm of FSR Gain = 12 −15 ±2 +15 ppm of FSR Gain > 14 Offset Error5 Before Calibration ±15 μV Gain = 1 to 8 200/gain μV Gain = 16 to 128 After Internal Calibration/System In order of Calibration noise Offset Error Drift vs. Temperature6 Low Power Mode 10 nV/°C Gain = 1 or gain > 16 80 nV/°C Gain = 2 to 8 40 nV/°C Gain = 16 Mid Power Mode 10 nV/°C Gain = 1 or gain > 16 40 nV/°C Gain = 2 to 8 20 nV/°C Gain = 16 Full Power Mode 10 nV/°C Gain Error5, 7 Before Internal Calibration −0.0025 +0.0025 % Gain = 1, TA = 25°C −0.3 % Gain > 1 After Internal Calibration −0.016 +0.004 +0.016 % Gain = 2 to 8, TA = 25°C ±0.025 % Gain = 16 to 128 After System Calibration In order of noise Gain Error Drift vs. Temperature 1 2 ppm/°C Power Supply Rejection AIN = 1 V/gain, external reference Low Power Mode 87 dB Gain = 2 to 16 96 dB Gain = 1 or gain > 16 Mid Power Mode2 92 dB Gain = 2 to 16 100 dB Gain = 1 or gain > 16 Full Power Mode 99 dB Common-Mode Rejection8 At DC2 85 90 dB AIN = 1 V, gain = 1 105 115 dB AIN = 1 V/gain, gain 2 or 4 1029, 2 dB AIN = 1 V/gain, gain 2 or 4 115 120 dB AIN = 1 V/gain, gain ≥ 8 1059, 2 dB AIN = 1 V/gain, gain ≥ 8 Sinc3, Sinc4 Filter2 At 50 Hz, 60 Hz 120 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz At 50 Hz 120 dB 50 SPS, 50 Hz ± 1 Hz At 60 Hz 120 dB 60 SPS, 60 Hz ± 1 Hz Rev. 0 | Page 4 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE