Datasheet AD7606-EP (Analog Devices) - 9

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Data Sheet AD7606-EP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ND ND ND ND ND ND ND ND 8G 7G 6G 5G 4G 3G 2G 1G V V8 V V7 V V6 V V5 V V4 V V3 V V2 V V1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVCC 1 48 AVCC ANALOG INPUT PIN 1 AGND 2 47 AGND DECOUPLING CAP PIN OS 0 3 46 REFGND POWER SUPPLY OS 1 4 45 REFCAPB GROUND PIN OS 2 5 44 REFCAPA 6 DATA OUTPUT PAR/SER/BYTE SEL AD7606-EP 43 REFGND 7 DIGITAL OUTPUT STBY TOP VIEW 42 REFIN/REFOUT (Not to Scale) RANGE 8 41 AGND DIGITAL INPUT 9 CONVST A 40 AGND REFERENCE INPUT/OUTPUT CONVST B 10 39 REGCAP RESET 11 38 AVCC RD/SCLK 12 37 AVCC 13 CS 36 REGCAP BUSY 14 35 AGND FRSTDATA 15 34 REF SELECT DB0 16 33 DB15/BYTE SEL 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 E A B N V ND DB1 DB2 DB3 DB4 DB5 DB6 UT UT DB9 DRI O O DB10 DB11 DB12 DB13 AG HBE V D D
008
DB7/ DB8/ DB14/
16483- Figure 4. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Type1 Mnemonic Description
1, 37, 38, 48 P AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front- end amplifiers and to the ADC core. Decouple these supply pins to AGND. 2, 26, 35, 40, P AGND Analog Ground. These pins are the ground reference points for all analog circuitry on the 41, 47 AD7606-EP. Refer all analog input signals and external reference signals to these pins. Connect the six AGND pins to the AGND plane of a system. 3, 4, 5 DI OS 0, OS 1, OS 2 Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2 is the most significant bit (MSB) control bit, and OS 0 is the least significant bit (LSB) control bit. See the Oversample Bit Decoding table and Digital Filter section in the AD7606 data sheet for more details about the logic states and oversampling mode of operation. 6 DI PAR/SER/ Paral el/Serial/Byte Interface Selection Input. Logic input. See the Interface Mode Selection BYTE SEL table in the AD7606 data sheet. If this pin is tied to a logic low, the paral el interface is selected. If this pin is tied to a logic high, the serial interface is selected. Paral el byte interface mode is selected when this pin is logic high and DB15/BYTE SEL is logic high. In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA pin and the DB8/DOUTB pin function as serial data outputs. When the serial interface is selected, tie the DB[15:9] and DB[6:0] pins to ground. In byte mode, DB15, in conjunction with PAR/SER/BYTE SEL, is used to select the parallel byte mode of operation. DB14 is used as the HBEN pin. DB[7:0] transfer the 16-bit conversion results in two RD operations, with DB0 as the LSB of the data transfers. 7 DI STBY Standby Mode Input. This pin is used to place the AD7606-EP into one of two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin. When in standby mode, al circuitry, except the on-chip reference, regulators, and regulator buffers, is powered down. When in shutdown mode, al circuitry is powered down. See the Power-Down Mode Selection table in the AD7606 data sheet. Rev. 0 | Page 9 of 15 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE