Datasheet AD7606-EP (Analog Devices) - 10

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AD7606-EP Data Sheet Pin No. Type1 Mnemonic Description
8 DI RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic change on this pin has an immediate effect on the analog input range. Changing this pin during a conversion is not recommended for fast throughput rate applications. See the Analog Input section in the AD7606 data sheet for more information. 9, 10 DI CONVST A, Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are CONVST B used to initiate conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A and CONVST B can be shorted together, and a single convert start signal can be applied. Alternatively, CONVST A can be used to initiate simultaneous sampling: V1, V2, V3, and V4 for the AD7606-EP. CONVST B can be used to initiate simultaneous sampling on the other analog inputs: V5, V6, V7, and V8 for the AD7606-EP. This is possible only when oversampling is not switched on. When the CONVST A or CONVST B pin transitions from low to high, the front-end, track-and-hold circuitry for the respective analog inputs is set to hold. 11 DI RESET Reset Input. When set to logic high, the rising edge of RESET resets the AD7606-EP. The device receives a RESET pulse directly after power-up. The RESET high pulse is typically 50 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers reset to all zeros. 12 DI RD/SCLK Paral el Data Read Control Input When Paral el Interface Selected (RD)/Serial Clock Input When Serial Interface Selected (SCLK). When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the DOUTA and DOUTB data output lines out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the DOUTA and DOUTB serial data outputs. See the Conversion Control section in the AD7606 data sheet for more information. 13 DI CS Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the DB[15:0] output bus is enabled, and the conversion result is output on the parallel data bus lines. In serial mode, CS is used to frame the serial read transfer and clock out the MSB of the serial output data. 14 DO BUSY Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and indicates that the conversion process has started. The BUSY output remains high until the conversion process for all channels is complete. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and is available to read after t4. Any data read while BUSY is high must be completed before the falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high. 15 DO FRSTDATA Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on the parallel, byte, or serial interface. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, indicating that the result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low following the next falling edge of RD. In serial mode, FRSTDATA goes high on the fal ing edge of CS because this pin clocks out the MSB of V1 on DOUTA. FRSTDATA returns low on the 16th SCLK falling edge after the CS falling edge. See the Conversion Control section in the AD7606 data sheet for more information. 22 to 16 DO DB[6:0] Parallel Output Data Bits, DB6 to DB0. When PAR/SER/BYTE SEL = 0, these pins act as three- state parallel digital input and output pins. When CS and RD are low, these pins are used to output DB6 to DB0 of the conversion result. When PAR/SER/BYTE SEL = 1, tie these pins to AGND. When operating in parallel byte interface mode, DB[7:0] outputs the 16-bit conversion result in two RD operations. DB7 (Pin 24) is the MSB and DB0 is the LSB. See Pin 24 description for additional information. 23 P VDRIVE Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the operating voltage of the interface. This pin is nominal y at the same supply as the supply of the host interface (that is, digital signal processor and field programmable gate array). Rev. 0 | Page 10 of 15 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE