Key Sheet AD7193 (Analog Devices) - 4

AD7193 Key Sheet Continuous Read Mode
conversion is available. When the user applies sufficient SCLK Rather than write to the communications register each time a pulses, the data is automatically placed on the DOUT/RDY pin. conversion is complete to access the data, the AD7193 can be
Single Conversion Mode
configured so that the conversions are automatical y placed on In single conversion mode, the AD7193 performs a single the DOUT/RDY line. By writing 01011100 to the communications conversion and is placed in standby mode after the conversion register, the user need only apply the appropriate number of is complete. DOUT/RDY goes low to indicate the completion of a SCLK cycles to the ADC, and the conversion word is automatical y conversion. When the data-word has been read from the data placed on the DOUT/RDY line when a conversion is complete. register, DOUT/RDY goes high. The data register can be read
CS
several times, if required, even when DOUT/RDY has gone high. If several channels are enabled, the ADC sequences through the enabled channels and performs a conversion on each channel.
DIN
When a conversion is started, DOUT/RDY goes high and remains
DATA DATA
high until a valid conversion is available. As soon as a conversion is
DOUT/RDY DATA
available, DOUT/RDY goes low. The ADC then selects the next channel and begins another conversion. The user can read the
SCLK
present conversion while the next conversion is being performed. Figure 5. Continuous Read Mode
CS
When DOUT/RDY goes low to indicate the end of a conversion, sufficient SCLK cycles must be applied to the ADC. The data
DATA REQUEST DIN
conversion is then placed on the DOUT/RDY line. When the conversion is read, DOUT/RDY returns high until the next con-
DATA DOUT/RDY
version is available. In this mode, the data can be read only once. When several channels are enabled, the ADC continuously loops through the enabled channels, performing one conversion
SCLK
on each channel per loop. DOUT/RDY pulses low when a Figure 6. Single Conversion Mode
TYPICAL APPLICATION DIAGRAM 5V AGND AV DV DD DD DGND REFIN1(+) REFERENCE IN+ DETECT AIN1 AVDD OUT– OUT+ AIN2 IN+ DOUT/RDY SERIAL IN– INTERFACE OUT– OUT+ AIN3 MUX DIN PGA Σ-Δ ADC AND AIN4 CONTROL SCLK AIN5 LOGIC CS IN– AIN6 SYNC AGND P1/REFIN2(+) P0/REFIN2(–) REFIN1(–) AD7193 BPDSW CLOCK CIRCUITRY AGND MCLK1 MCLK2
Figure 7. Typical Application Diagram Rev. 0 | Page 4 of 6 Document Outline General Description Features and Benefits Key Characteristics Fundamental Specifications Noise Sinc4 Chop Disabled Filter Setting Fast Settling Filter Setting Operating the AD7193 Data Interface 4-Wire Serial Interface 3-Wire Serial Interface Data Modes Continuous Conversion Mode (Default) Continuous Read Mode Single Conversion Mode Typical Application Diagram Frequently Asked Questions Learn More and Start Designing Compatible Devices Package Diagram Getting Started