Datasheet AD7689-KGD (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 8-Channel,250 kSPS PulSAR ADC |
| 页数 / 页 | 10 / 6 — AD7689-KGD. Known Good Die. TIMING SPECIFICATIONS. Table 3. Parameter1. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 224 Kb |
| 文件语言 | 英语 |
AD7689-KGD. Known Good Die. TIMING SPECIFICATIONS. Table 3. Parameter1. Symbol. Min. Typ. Max. Unit
该数据表的模型线
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AD7689-KGD Known Good Die TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter1 Symbol Min Typ Max Unit
CONVERSION TIME tCONV CNV Rising Edge to Data Available 2.4 µs ACQUISITION TIME tACQ 1.8 µs TIME BETWEEN CONVERSIONS tCYC 4.0 µs DATA WRITE/READ DURING CONVERSION tDATA 1.2 µs SCK Period tSCK tDSDO + 2 ns Low Time tSCKL 11 ns High Time tSCKH 11 ns Falling Edge to Data Remains Valid tHSDO 4 ns Falling Edge to Data Valid Delay tDSDO VIO Above 2.7 V 18 ns VIO Above 2.3 V 23 ns VIO Above 1.8 V 28 ns CNV Pulse Width tCNVH 10 ns Low to SDO D15 MSB Valid tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns VIO Above 1.8 V 25 ns High or Last SCK Falling Edge to SDO High Impedance tDIS 32 ns Low to SCK Rising Edge tCLSCK 10 ns DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns Valid Hold Time from SCK Rising Edge tHDIN 5 ns 1 See Figure 2 and Figure 3 for load conditions. Rev. C | Page 6 of 10 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE
AD7689-KGD Known Good Die TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter1 Symbol Min Typ Max Unit
CONVERSION TIME tCONV CNV Rising Edge to Data Available 2.4 µs ACQUISITION TIME tACQ 1.8 µs TIME BETWEEN CONVERSIONS tCYC 4.0 µs DATA WRITE/READ DURING CONVERSION tDATA 1.2 µs SCK Period tSCK tDSDO + 2 ns Low Time tSCKL 11 ns High Time tSCKH 11 ns Falling Edge to Data Remains Valid tHSDO 4 ns Falling Edge to Data Valid Delay tDSDO VIO Above 2.7 V 18 ns VIO Above 2.3 V 23 ns VIO Above 1.8 V 28 ns CNV Pulse Width tCNVH 10 ns Low to SDO D15 MSB Valid tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns VIO Above 1.8 V 25 ns High or Last SCK Falling Edge to SDO High Impedance tDIS 32 ns Low to SCK Rising Edge tCLSCK 10 ns DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns Valid Hold Time from SCK Rising Edge tHDIN 5 ns 1 See Figure 2 and Figure 3 for load conditions. Rev. C | Page 6 of 10 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE