Datasheet LTC1863, LTC1867 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 8-Channel 200ksps ADCs |
| 页数 / 页 | 18 / 8 — PIN FUNCTIONS CHO-CH7/COM (Pins 1-8):. SDO (Pin 13):. SDI (Pin 14):. … |
| 修订版 | E |
| 文件格式/大小 | PDF / 470 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS CHO-CH7/COM (Pins 1-8):. SDO (Pin 13):. SDI (Pin 14):. REFCOMP (Pin 9):. GND (Pin 15):. VDD (Pin 16):. VREF (Pin 10):
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文件文字版本
LTC1863/LTC1867
PIN FUNCTIONS CHO-CH7/COM (Pins 1-8):
Analog Input Pins. Analog
SDO (Pin 13):
Digital Data Output. The A/D conversion result inputs must be free of noise with respect to GND. CH7/ is shifted out of this output. Straight binary format for uni- COM can be either a separate channel or the common polar mode and two’s complement format for bipolar mode. minus input for the other channels.
SDI (Pin 14):
Digital Data Input Pin. The A/D configuration
REFCOMP (Pin 9):
Reference Buffer Output Pin. Bypass word is shifted into this input. to GND with a 10µF tantalum capacitor in parallel with a
GND (Pin 15):
Analog and Digital GND. 0.1µF ceramic capacitor (4.096V Nominal). To overdrive REFCOMP, tie VREF to GND.
VDD (Pin 16):
Analog and Digital Power Supply. Bypass to GND with a 10µF tantalum capacitor in parallel with a
VREF (Pin 10):
2.5V Reference Output. This pin can also 0.1µF ceramic capacitor. When powering up the LTC1863/ be used as an external reference buffer input for improved LTC1867, or any time V accuracy and drift. Bypass to GND with a 2.2µF tantalum DD falls below the minimum speci- fied operating voltage, one dummy conversion must be capacitor in parallel with a 0.1µF ceramic capacitor. initiated by providing a rising edge on the CS/CONV pin.
CS/CONV (Pin 11):
This input provides the dual function The first conversion result may be invalid and should be of initiating conversions on the ADC and also frames the ignored. Once the CS/CONV pin is returned low, a DIN serial data transfer. word can be shifted into SDI to program the configura-
SCK (Pin 12):
Shift Clock. This clock synchronizes the tion for the next conversion. Wait at least t7, the SLEEP serial data transfer. mode wake-up time of 80ms, before initiating the second conversion to obtain a valid conversion result.
TYPICAL CONNECTION DIAGRAM
±2.048V + CH0 VDD 5V DIFFERENTIAL INPUTS – CH1 GND CH2 SDI LTC1863/ CH3 LTC1867 SDO DIGITAL 4.096V SINGLE-ENDED + I/O CH4 SCK INPUT CH5 CS/CONV CH6 VREF 2.5V CH7/COM REFCOMP 4.096V 2.2µF 10µF 18637 TCD
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 3k 3k DN DN DN DN 3k CL CL 3k CL CL (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 18637 TC01 18637 TC02 Rev. E 8 For more information www.analog.com Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Dynamic Accuracy Analog Input Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Typical Connection Diagram Test Circuits Timing Diagrams Applications Information Package Description Revision History Related Parts
PIN FUNCTIONS CHO-CH7/COM (Pins 1-8):
Analog Input Pins. Analog
SDO (Pin 13):
Digital Data Output. The A/D conversion result inputs must be free of noise with respect to GND. CH7/ is shifted out of this output. Straight binary format for uni- COM can be either a separate channel or the common polar mode and two’s complement format for bipolar mode. minus input for the other channels.
SDI (Pin 14):
Digital Data Input Pin. The A/D configuration
REFCOMP (Pin 9):
Reference Buffer Output Pin. Bypass word is shifted into this input. to GND with a 10µF tantalum capacitor in parallel with a
GND (Pin 15):
Analog and Digital GND. 0.1µF ceramic capacitor (4.096V Nominal). To overdrive REFCOMP, tie VREF to GND.
VDD (Pin 16):
Analog and Digital Power Supply. Bypass to GND with a 10µF tantalum capacitor in parallel with a
VREF (Pin 10):
2.5V Reference Output. This pin can also 0.1µF ceramic capacitor. When powering up the LTC1863/ be used as an external reference buffer input for improved LTC1867, or any time V accuracy and drift. Bypass to GND with a 2.2µF tantalum DD falls below the minimum speci- fied operating voltage, one dummy conversion must be capacitor in parallel with a 0.1µF ceramic capacitor. initiated by providing a rising edge on the CS/CONV pin.
CS/CONV (Pin 11):
This input provides the dual function The first conversion result may be invalid and should be of initiating conversions on the ADC and also frames the ignored. Once the CS/CONV pin is returned low, a DIN serial data transfer. word can be shifted into SDI to program the configura-
SCK (Pin 12):
Shift Clock. This clock synchronizes the tion for the next conversion. Wait at least t7, the SLEEP serial data transfer. mode wake-up time of 80ms, before initiating the second conversion to obtain a valid conversion result.
TYPICAL CONNECTION DIAGRAM
±2.048V + CH0 VDD 5V DIFFERENTIAL INPUTS – CH1 GND CH2 SDI LTC1863/ CH3 LTC1867 SDO DIGITAL 4.096V SINGLE-ENDED + I/O CH4 SCK INPUT CH5 CS/CONV CH6 VREF 2.5V CH7/COM REFCOMP 4.096V 2.2µF 10µF 18637 TCD
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 3k 3k DN DN DN DN 3k CL CL 3k CL CL (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 18637 TC01 18637 TC02 Rev. E 8 For more information www.analog.com Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Dynamic Accuracy Analog Input Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Typical Connection Diagram Test Circuits Timing Diagrams Applications Information Package Description Revision History Related Parts