Datasheet AD7768-1 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | DC to 204 kHz, Dynamic Signal Analysis, Precision 24-Bit ADC with Power Scaling |
| 页数 / 页 | 80 / 2 — AD7768-1. Data Sheet. TABLE OF CONTENTS |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.8 Mb |
| 文件语言 | 英语 |
AD7768-1. Data Sheet. TABLE OF CONTENTS
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AD7768-1 Data Sheet TABLE OF CONTENTS
Features .. 1 Electromagnetic Compatibility (EMC) Testing ... 64 Applications ... 1 AD7768-1 Subsystem Layout ... 65 Functional Block Diagram .. 1 Register Summary .. 66 Revision History ... 3 Register Details ... 68 General Description ... 4 Component Type Register ... 68 Specifications ... 5 Unique Product ID Registers .. 68 3 V Operation.. 10 Device Grade and Revision Register ... 68 Timing Specifications .. 11 User Scratchpad Register ... 68 1.8 V Timing Specifications .. 12 Device Vendor ID Registers .. 68 Absolute Maximum Ratings .. 17 Interface Format Control Register ... 69 Thermal Resistance .. 17 Power and Clock Control Register... 69 ESD Caution .. 17 Analog Buffer Control Register .. 70 Pin Configuration and Function Descriptions ... 18 VCM Control Register ... 71 Typical Performance Characteristics ... 20 Conversion Source Select and Mode Control Register ... 71 Terminology .. 28 Digital Filter and Decimation Control Register ... 72 Theory of Operation .. 29 Sinc3 Decimation Rate (MSB Register) .. 73 Clocking, Sampling Tree, and Power Scaling ... 29 Sinc3 Decimation Rate (LSB Register) .. 73 Noise Performance and Resolution.. 30 Periodic Conversion Rate Control Register .. 73 Core Converter ... 32 Synchronization Modes and Reset Triggering Register .. 74 Clocking and Clock Selection ... 35 GPIO Port Control Register .. 74 Digital Filtering ... 35 GPIO Output Control Register .. 75 Decimation Rate Control .. 40 GPIO Input Read Register .. 75 Antialiasing Filtering ... 40 Offset Calibration MSB Register .. 75 Getting Started .. 41 Offset Calibration MID Register .. 75 Power Supplies .. 43 Offset Calibration LSB Register ... 76 Device Configuration Method ... 43 Gain Calibration MSB Register .. 76 Pin Control Mode Overview .. 44 Gain Calibration MID Register .. 76 SPI Control Overview .. 47 Gain Calibration LSB Register .. 76 SPI Control Mode ... 48 SPI Interface Diagnostic Control Register .. 77 Digital Interface .. 51 ADC Diagnostic Feature Control Register ... 77 Data Conversion Modes .. 55 Digital Diagnostic Feature Control Register .. 77 Synchronization of Multiple AD7768-1 Devices .. 56 Conversion Result Register ... 77 Additional Functionality of the AD7768-1 ... 58 Device Error Flags Master Register ... 78 Applications Information .. 59 SPI Interface Error Register .. 78 Analog Input Recommendations ... 59 ADC Diagnostics Output Register ... 78 Antialiasing Filter Design Considerations .. 60 Digital Diagnostics Output Register .. 79 Recommended Interface ... 61 MCLK Diagnostic Output Register ... 79 Programmable Digital Filter ... 62 Coefficient Control Register ... 79 Rev. A | Page 2 of 80 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 3 V OPERATION TIMING SPECIFICATIONS 1.8 V TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Power vs. Noise Performance Optimization Example of Power vs. Noise Performance Optimization Configuration A Configuration B NOISE PERFORMANCE AND RESOLUTION CORE CONVERTER ADC Core and Signal Chain Analog Inputs and Precharge Buffering VCM Output Reference Input and Buffering CLOCKING AND CLOCK SELECTION CLKSEL Pin Using the Internal Oscillator DIGITAL FILTERING Sinc5 Filter Sinc3 Filter Programming for 50 Hz, 60 Hz, and 50 Hz and 60 Hz Rejection Low Ripple FIR Filter DECIMATION RATE CONTROL ANTIALIASING FILTERING Modulator Saturation Point Modulator Unprotected Zones Modulator Chopping Frequency GETTING STARTED Method of Configuration—PINB Control Mode or SPI Control Mode Digital Filter Type and Decimation Power Mode POWER SUPPLIES Single-Supply Mode Recommended Power Supply Configuration DEVICE CONFIGURATION METHOD PINB Configuration SPI Control PIN CONTROL MODE OVERVIEW Power Mode Data Output Format Diagnostics and Status Bits Daisy-Chaining—PINB Control Mode Only SPI CONTROL OVERVIEW SPI CONTROL MODE MCLK Source and MCLK Division Power-Down Mode Standby Mode SPI Synchronization Offset Calibration Gain Calibration Reset over SPI Control Interface Resume from Shutdown GPIO and STARTB Functions SPI Mode Diagnostic Features Reference Detection Clock Qualification CRC on SPI Transaction Flags for Detection of Illegal Register Write CRC Checks POR Monitor MCLK Counter Product Identification (ID) Number DIGITAL INTERFACE SPI Reading and Writing SPI Control Interface Error Handling CRC Check on Serial Interface Conversion Read Modes Single-Conversion Read Mode Continuous Read Mode Exiting Continuous Read Mode DATA CONVERSION MODES Continuous Conversion Mode One Shot Conversion Mode Single-Conversion Mode Duty Cycled Conversion Mode SYNCHRONIZATION OF MULTIPLE AD7768-1 DEVICES ADDITIONAL FUNCTIONALITY OF THE AD7768-1 Reset Status Header Diagnostics APPLICATIONS INFORMATION ANALOG INPUT RECOMMENDATIONS Recommended Driver Amplifiers ANTIALIASING FILTER DESIGN CONSIDERATIONS RECOMMENDED INTERFACE Initializing the Recommended Interface Recommended Interface for Reading Data Resynchronization of the Recommended Interface PROGRAMMABLE DIGITAL FILTER Filter Coefficients Upload Sequence Example Filter Upload Filter Upload Verification ELECTROMAGNETIC COMPATIBILITY (EMC) TESTING Radiated Immunity Radiated Emissions Electrical Fast Transients (EFTs) AD7768-1 SUBSYSTEM LAYOUT REGISTER SUMMARY REGISTER DETAILS COMPONENT TYPE REGISTER UNIQUE PRODUCT ID REGISTERS DEVICE GRADE AND REVISION REGISTER USER SCRATCHPAD REGISTER DEVICE VENDOR ID REGISTERS INTERFACE FORMAT CONTROL REGISTER POWER AND CLOCK CONTROL REGISTER ANALOG BUFFER CONTROL REGISTER VCM CONTROL REGISTER CONVERSION SOURCE SELECT AND MODE CONTROL REGISTER DIGITAL FILTER AND DECIMATION CONTROL REGISTER SINC3 DECIMATION RATE (MSB REGISTER) SINC3 DECIMATION RATE (LSB REGISTER) PERIODIC CONVERSION RATE CONTROL REGISTER SYNCHRONIZATION MODES AND RESET TRIGGERING REGISTER GPIO PORT CONTROL REGISTER GPIO OUTPUT CONTROL REGISTER GPIO INPUT READ REGISTER OFFSET CALIBRATION MSB REGISTER OFFSET CALIBRATION MID REGISTER OFFSET CALIBRATION LSB REGISTER GAIN CALIBRATION MSB REGISTER GAIN CALIBRATION MID REGISTER GAIN CALIBRATION LSB REGISTER SPI INTERFACE DIAGNOSTIC CONTROL REGISTER ADC DIAGNOSTIC FEATURE CONTROL REGISTER DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER CONVERSION RESULT REGISTER DEVICE ERROR FLAGS MASTER REGISTER SPI INTERFACE ERROR REGISTER ADC DIAGNOSTICS OUTPUT REGISTER DIGITAL DIAGNOSTICS OUTPUT REGISTER MCLK DIAGNOSTIC OUTPUT REGISTER COEFFICIENT CONTROL REGISTER COEFFICIENT DATA REGISTER ACCESS KEY REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
AD7768-1 Data Sheet TABLE OF CONTENTS
Features .. 1 Electromagnetic Compatibility (EMC) Testing ... 64 Applications ... 1 AD7768-1 Subsystem Layout ... 65 Functional Block Diagram .. 1 Register Summary .. 66 Revision History ... 3 Register Details ... 68 General Description ... 4 Component Type Register ... 68 Specifications ... 5 Unique Product ID Registers .. 68 3 V Operation.. 10 Device Grade and Revision Register ... 68 Timing Specifications .. 11 User Scratchpad Register ... 68 1.8 V Timing Specifications .. 12 Device Vendor ID Registers .. 68 Absolute Maximum Ratings .. 17 Interface Format Control Register ... 69 Thermal Resistance .. 17 Power and Clock Control Register... 69 ESD Caution .. 17 Analog Buffer Control Register .. 70 Pin Configuration and Function Descriptions ... 18 VCM Control Register ... 71 Typical Performance Characteristics ... 20 Conversion Source Select and Mode Control Register ... 71 Terminology .. 28 Digital Filter and Decimation Control Register ... 72 Theory of Operation .. 29 Sinc3 Decimation Rate (MSB Register) .. 73 Clocking, Sampling Tree, and Power Scaling ... 29 Sinc3 Decimation Rate (LSB Register) .. 73 Noise Performance and Resolution.. 30 Periodic Conversion Rate Control Register .. 73 Core Converter ... 32 Synchronization Modes and Reset Triggering Register .. 74 Clocking and Clock Selection ... 35 GPIO Port Control Register .. 74 Digital Filtering ... 35 GPIO Output Control Register .. 75 Decimation Rate Control .. 40 GPIO Input Read Register .. 75 Antialiasing Filtering ... 40 Offset Calibration MSB Register .. 75 Getting Started .. 41 Offset Calibration MID Register .. 75 Power Supplies .. 43 Offset Calibration LSB Register ... 76 Device Configuration Method ... 43 Gain Calibration MSB Register .. 76 Pin Control Mode Overview .. 44 Gain Calibration MID Register .. 76 SPI Control Overview .. 47 Gain Calibration LSB Register .. 76 SPI Control Mode ... 48 SPI Interface Diagnostic Control Register .. 77 Digital Interface .. 51 ADC Diagnostic Feature Control Register ... 77 Data Conversion Modes .. 55 Digital Diagnostic Feature Control Register .. 77 Synchronization of Multiple AD7768-1 Devices .. 56 Conversion Result Register ... 77 Additional Functionality of the AD7768-1 ... 58 Device Error Flags Master Register ... 78 Applications Information .. 59 SPI Interface Error Register .. 78 Analog Input Recommendations ... 59 ADC Diagnostics Output Register ... 78 Antialiasing Filter Design Considerations .. 60 Digital Diagnostics Output Register .. 79 Recommended Interface ... 61 MCLK Diagnostic Output Register ... 79 Programmable Digital Filter ... 62 Coefficient Control Register ... 79 Rev. A | Page 2 of 80 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 3 V OPERATION TIMING SPECIFICATIONS 1.8 V TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Power vs. Noise Performance Optimization Example of Power vs. Noise Performance Optimization Configuration A Configuration B NOISE PERFORMANCE AND RESOLUTION CORE CONVERTER ADC Core and Signal Chain Analog Inputs and Precharge Buffering VCM Output Reference Input and Buffering CLOCKING AND CLOCK SELECTION CLKSEL Pin Using the Internal Oscillator DIGITAL FILTERING Sinc5 Filter Sinc3 Filter Programming for 50 Hz, 60 Hz, and 50 Hz and 60 Hz Rejection Low Ripple FIR Filter DECIMATION RATE CONTROL ANTIALIASING FILTERING Modulator Saturation Point Modulator Unprotected Zones Modulator Chopping Frequency GETTING STARTED Method of Configuration—PINB Control Mode or SPI Control Mode Digital Filter Type and Decimation Power Mode POWER SUPPLIES Single-Supply Mode Recommended Power Supply Configuration DEVICE CONFIGURATION METHOD PINB Configuration SPI Control PIN CONTROL MODE OVERVIEW Power Mode Data Output Format Diagnostics and Status Bits Daisy-Chaining—PINB Control Mode Only SPI CONTROL OVERVIEW SPI CONTROL MODE MCLK Source and MCLK Division Power-Down Mode Standby Mode SPI Synchronization Offset Calibration Gain Calibration Reset over SPI Control Interface Resume from Shutdown GPIO and STARTB Functions SPI Mode Diagnostic Features Reference Detection Clock Qualification CRC on SPI Transaction Flags for Detection of Illegal Register Write CRC Checks POR Monitor MCLK Counter Product Identification (ID) Number DIGITAL INTERFACE SPI Reading and Writing SPI Control Interface Error Handling CRC Check on Serial Interface Conversion Read Modes Single-Conversion Read Mode Continuous Read Mode Exiting Continuous Read Mode DATA CONVERSION MODES Continuous Conversion Mode One Shot Conversion Mode Single-Conversion Mode Duty Cycled Conversion Mode SYNCHRONIZATION OF MULTIPLE AD7768-1 DEVICES ADDITIONAL FUNCTIONALITY OF THE AD7768-1 Reset Status Header Diagnostics APPLICATIONS INFORMATION ANALOG INPUT RECOMMENDATIONS Recommended Driver Amplifiers ANTIALIASING FILTER DESIGN CONSIDERATIONS RECOMMENDED INTERFACE Initializing the Recommended Interface Recommended Interface for Reading Data Resynchronization of the Recommended Interface PROGRAMMABLE DIGITAL FILTER Filter Coefficients Upload Sequence Example Filter Upload Filter Upload Verification ELECTROMAGNETIC COMPATIBILITY (EMC) TESTING Radiated Immunity Radiated Emissions Electrical Fast Transients (EFTs) AD7768-1 SUBSYSTEM LAYOUT REGISTER SUMMARY REGISTER DETAILS COMPONENT TYPE REGISTER UNIQUE PRODUCT ID REGISTERS DEVICE GRADE AND REVISION REGISTER USER SCRATCHPAD REGISTER DEVICE VENDOR ID REGISTERS INTERFACE FORMAT CONTROL REGISTER POWER AND CLOCK CONTROL REGISTER ANALOG BUFFER CONTROL REGISTER VCM CONTROL REGISTER CONVERSION SOURCE SELECT AND MODE CONTROL REGISTER DIGITAL FILTER AND DECIMATION CONTROL REGISTER SINC3 DECIMATION RATE (MSB REGISTER) SINC3 DECIMATION RATE (LSB REGISTER) PERIODIC CONVERSION RATE CONTROL REGISTER SYNCHRONIZATION MODES AND RESET TRIGGERING REGISTER GPIO PORT CONTROL REGISTER GPIO OUTPUT CONTROL REGISTER GPIO INPUT READ REGISTER OFFSET CALIBRATION MSB REGISTER OFFSET CALIBRATION MID REGISTER OFFSET CALIBRATION LSB REGISTER GAIN CALIBRATION MSB REGISTER GAIN CALIBRATION MID REGISTER GAIN CALIBRATION LSB REGISTER SPI INTERFACE DIAGNOSTIC CONTROL REGISTER ADC DIAGNOSTIC FEATURE CONTROL REGISTER DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER CONVERSION RESULT REGISTER DEVICE ERROR FLAGS MASTER REGISTER SPI INTERFACE ERROR REGISTER ADC DIAGNOSTICS OUTPUT REGISTER DIGITAL DIAGNOSTICS OUTPUT REGISTER MCLK DIAGNOSTIC OUTPUT REGISTER COEFFICIENT CONTROL REGISTER COEFFICIENT DATA REGISTER ACCESS KEY REGISTER OUTLINE DIMENSIONS ORDERING GUIDE