Datasheet AD7790 (Analog Devices) - 3

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Key Sheet AD7790 OPERATING THE AD7790 DATA INTERFACE
the data register. When the data-word has been read from the data register, DOUT/RDY goes high. The user can read this register The data interface for the AD7790 is additional times, if required. • Performed using a 4- or 3-wire SPI •
CS
Compatible with SPI, QSPI, MICROWIRE, and DSP • Al ows a user to both write to and read from the AD7790 on the same data bus
DIN DATA DATA REQUEST REQUEST
• Indicates when transferred data is available by bringing the DOUT/RDY signal and the RDY bit in the status register low
DATA DOUT/RDY DATA AD7790 (SLAVE)
003
SCLK
11264-
CS1
Figure 3. Continuous Conversion Mode
SCLK DSP/FPGA/ Continuous Read Mode MICROCONTROLLER DOUT/RDY
Rather than write to the communications register each time a conversion is complete to access the data, the AD7790 can be
DIN
configured so that the conversions are automatical y placed on the DOUT/RDY line. By writing 001111XX (where XX represent
1CS IS PERMANENTLY TIED LOW IN THE 3-WIRE INTERFACE.
002
(IF CS IS REQUIRED AS A DECODING SIGNAL, IT CAN BE
don’t cares) to the communications register, the user need only
GENERATED FROM A PORT PIN.)
11264- apply the appropriate number of SCLK cycles to the ADC, and Figure 2. AD7790 Data Interface, 4-Wire SPI the conversion word is automatical y placed on the DOUT/RDY
Table 3. 4-Wire Serial Interface Pin Functions
line when a conversion is complete.
Pin Function CS
CS1 Selects the ADC (also applicable in systems with multiple devices on the serial bus). Provides a frame synchronization signal.2
DIN
SCLK Determines when data transfers (either on DIN or DOUT/RDY) occur.
DOUT/RDY DATA DATA DATA
DOUT/RDY Accesses data from the on-chip registers. Indicates when the transferred data is available. 006 DIN Transfers data into the on-chip registers.
SCLK
11264- Figure 4. Continuous Read Mode 1 CS is permanently tied low in the 3-wire interface. (If CS is required as a decoding signal, it can be generated from a port pin.) In continuous read mode, the serial interface is dedicated to 2 Useful for DSP interfaces. The first bit (MSB) is effectively clocked out by CS reads of the data register. If any other register needs to be because CS typically occurs after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers accessed, continuous read mode must be disabled. In addition, are obeyed. every time a conversion is available, the serial interface is reset in this mode. Therefore, it is essential that the conversion be
DATA MODES
read before the next conversion is available. There are three data modes available: continuous conversion While in the continuous read mode, the ADC monitors activity mode, continuous read mode, and single conversion mode. on the DIN line so that it can receive the instruction to exit the
Continuous Conversion Mode (Default)
continuous read mode. Additionally, a reset occurs if 32 consec- Continuous conversion is the default power-up mode. In this utive 1s are seen on DIN. Therefore, DIN should be held low in mode, the AD7790 converts continuously, and the RDY bit in continuous read mode until an instruction is to be written to the status register goes low each time a conversion is complete. the device. If CS is low, the DOUT/RDY line also goes low when a conversion is complete. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of Rev. 0 | Page 3 of 6 Document Outline General Description Features and Benefits Key Characteristics Fundamental Specifications Noise Operating the AD7790 Data Interface Data Modes Continuous Conversion Mode (Default) Continuous Read Mode Single Conversion Mode Typical Application Diagram Frequently Asked Questions Learn More and Start Designing Compatible Devices Package Diagram Getting Started