Datasheet LTM2173-14 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 80Msps Low Power Quad ADC |
| 页数 / 页 | 28 / 7 — TIMING CHARACTERISTICS. Note 7:. Note 10:. Note 11:. Note 8:. Note 9:. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 414 Kb |
| 文件语言 | 英语 |
TIMING CHARACTERISTICS. Note 7:. Note 10:. Note 11:. Note 8:. Note 9:. Note 12:. TIMING DIAGRAMS
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LTM2173-14
TIMING CHARACTERISTICS Note 7:
Offset error is the offset voltage measured from –0.5 LSB when
Note 10:
Recommended operating conditions. the output code flickers between 00 0000 0000 0000 and 11 1111 1111
Note 11:
The maximum sampling frequency depends on the speed grade 1111 in 2’s complement output mode. of the part and also which serialization mode is used. The maximum serial
Note 8:
Guaranteed by design, not subject to test. data rate is 1000Mbps so tSER must be greater than or equal to 1ns.
Note 9:
VDD = OVDD = 1.8V, fSAMPLE = 80MHz, 2-lane output mode,
Note 12:
Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to Ch.4. differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with Far-channel crosstalk refers to Ch.1 to Ch.3, Ch.1 to Ch.4, Ch.2 to Ch.3, and differential drive, unless otherwise noted. The supply current and power Ch.2 to Ch.4. dissipation specifications are totals for the entire device, not per channel.
TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization*
tAP N+1 ANALOG N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 OUT#A+ OUT#B– D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217314 TD01 *SEE THE DIGITAL OUTPUTS SECTION
2-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+2 N INPUT t N+1 ENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 OUT#A+ OUT#B– D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 217314 TD02 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– Rev. A For more information www.analog.com 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Pin Functions Pin Configuration Table Functional Block Diagram Applications Information Package Description Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Pin Configuration Table Functional Block Diagram Applications Information Converter Operation Analog Input Input Drive Circuits Digital Outputs Data Format Device Programming Modes Grounding and Bypassing Heat Transfer Package Description Revision History Typical Application Related Parts
TIMING CHARACTERISTICS Note 7:
Offset error is the offset voltage measured from –0.5 LSB when
Note 10:
Recommended operating conditions. the output code flickers between 00 0000 0000 0000 and 11 1111 1111
Note 11:
The maximum sampling frequency depends on the speed grade 1111 in 2’s complement output mode. of the part and also which serialization mode is used. The maximum serial
Note 8:
Guaranteed by design, not subject to test. data rate is 1000Mbps so tSER must be greater than or equal to 1ns.
Note 9:
VDD = OVDD = 1.8V, fSAMPLE = 80MHz, 2-lane output mode,
Note 12:
Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to Ch.4. differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with Far-channel crosstalk refers to Ch.1 to Ch.3, Ch.1 to Ch.4, Ch.2 to Ch.3, and differential drive, unless otherwise noted. The supply current and power Ch.2 to Ch.4. dissipation specifications are totals for the entire device, not per channel.
TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization*
tAP N+1 ANALOG N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 OUT#A+ OUT#B– D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217314 TD01 *SEE THE DIGITAL OUTPUTS SECTION
2-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+2 N INPUT t N+1 ENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 OUT#A+ OUT#B– D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 217314 TD02 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– Rev. A For more information www.analog.com 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Pin Functions Pin Configuration Table Functional Block Diagram Applications Information Package Description Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Pin Configuration Table Functional Block Diagram Applications Information Converter Operation Analog Input Input Drive Circuits Digital Outputs Data Format Device Programming Modes Grounding and Bypassing Heat Transfer Package Description Revision History Typical Application Related Parts