Datasheet LTM2173-14 (Analog Devices) - 6

link to page 2 LTM2173-14
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTM2173-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Notes 10,11) l 5 80 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 5.93 6.25 100 ns Duty Cycle Stabilizer On l 2 6.25 100 ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 5.93 6.25 100 ns Duty Cycle Stabilizer On l 2 6.25 100 ns tAP Sample-and-Hold 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 1/(8 • fS) s 2-Lanes, 14-Bit Serialization 1/(7 • fS) s 2-Lanes, 12-Bit Serialization 1/(6 • fS) s 1-Lane, 16-Bit Serialization 1/(16 • fS) s 1-Lane, 14-Bit Serialization 1/(14 • fS) s 1-Lane, 12-Bit Serialization 1/(12 • fS) s tFRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tDATA DATA to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tPD Propagation Delay (Note 8) l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P Pipeline Latency 6 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Read Back Mode, CSDO = 20pF, l 250 ns RPULLUP = 2k tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Read Back Mode, CSDO = 20pF, l 125 ns RPULLUP = 2k
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
When these pin voltages are taken below GND they will be may cause permanent damage to the device. Exposure to any Absolute clamped by internal diodes. When these pin voltages are taken above VDD Maximum Rating condition for extended periods may affect device they will not be clamped by internal diodes. This product can handle input reliability and lifetime. currents of greater than 100mA below GND without latchup.
Note 2:
All voltage values are with respect to GND (unless otherwise
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 80MHz, 2-lane output mode, noted). differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with
Note 3:
When these pin voltages are taken below GND or above V differential drive, unless otherwise noted. DD, they will be clamped by internal diodes. This product can handle input currents
Note 6:
Integral nonlinearity is defined as the deviation of a code from a of greater than 100mA below GND or above VDD without latchup. best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Rev. A 6 For more information www.analog.com Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Pin Functions Pin Configuration Table Functional Block Diagram Applications Information Package Description Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Pin Configuration Table Functional Block Diagram Applications Information Converter Operation Analog Input Input Drive Circuits Digital Outputs Data Format Device Programming Modes Grounding and Bypassing Heat Transfer Package Description Revision History Typical Application Related Parts