Datasheet AD9690 (Analog Devices) - 9

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Data Sheet AD9690 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit
CLK+ to SYSREF+ TIMING REQUIREMENTS See Figure 3 tSU_SR Device clock to SYSREF+ setup time 117 ps tH_SR Device clock to SYSREF+ hold time −96 ps SPI TIMING REQUIREMENTS See Figure 4 tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK must be in a logic high state 10 ns tLOW Minimum period that SCLK must be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an 10 ns output relative to the SCLK falling edge (not shown in Figure 4) tDIS_SDIO Time required for the SDIO pin to switch from an output to an 10 ns input relative to the SCLK rising edge (not shown in Figure 4)
Timing Diagrams APERTURE DELAY SAMPLE N ANALOG INPUT N – 54 N + 1 N – 55 SIGNAL N – 53 N – 52 N – 51 N – 1 CLK– CLK+ CLK– CLK+ SERDOUT0– A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 MSB SERDOUT0+ SERDOUT1– A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 LSB SERDOUT1+ SAMPLE N – 55 SAMPLE N – 54 SAMPLE N – 53
002
ENCODED INTO 1 ENCODED INTO 1 ENCODED INTO 1 8-BIT/10-BIT SYMBOL 8-BIT/10-BIT SYMBOL 8-BIT/10-BIT SYMBOL
12834- Figure 2. Data Output Timing (Full Bandwidth Mode; L = 2; M = 1; F = 1)
CLK– CLK+ tSU_SR tH_SR SYSREF–
003
SYSREF+
12834- Figure 3. SYSREF± Setup and Hold Timing Rev. B | Page 9 of 78 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9690-1000 AD9690-500 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing Voltage Reference Clock Input Considerations Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC Overrange and Fast Detect ADC Overrange Fast Threshold Detection (FD) Signal Monitor SPORT Over JESD204B Digital Downconverter (DDC) DDC I/Q Input Selection DDC I/Q Output Selection DDC General Description Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Plus Mixer Loss and SFDR Numerically Controlled Oscillator Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR Filters General Description Half-Band Filters HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC Gain Stage DDC Complex—Real Conversion DDC Example Configurations Digital Outputs Introduction to the JESD204B Interface JESD204B Overview Functional Overview Transport Layer Data Link Layer Physical Layer JESD204B Link Establishment Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder Physical Layer (Driver) Outputs Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B Tx Converter Mapping Configuring the JESD204B Link Multichip Synchronization SYSREF± Setup/Hold Window Monitor Test Modes ADC Test Modes JESD204B Block Test Modes Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes Serial Port Interface Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels SPI Soft Reset Memory Map Register Table Applications Information Power Supply Recommendations Exposed Pad Thermal Heat Slug Recommendations AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) Outline Dimensions Ordering Guide