Datasheet AD9234 (Analog Devices) - 6

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AD9234 Data Sheet AD9234-500 AD9234-1000 Parameter Temperature Min Typ Max Min Typ Max Unit
POWER CONSUMPTION Total Power Dissipation (Including Output Drivers)2 Full 2.15 2.5 3.0 3.3 W Total Power Dissipation (L = 2 Mode) 25°C 2.08 N/A3 W Power-Down Dissipation Full 670 750 mW Standby4 Full 1.1 1.25 W 1 All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used. 2 Default mode. No DDCs used. L = 4, M = 2, F = 1. 3 N/A = not applicable. At the maximum sample rate, it is not applicable to use L = 2 mode on the JESD204B output interface because this exceeds the maximum lane rate of 12.5 Gbps. L = 2 mode is supported when the equation ((M × N΄ × (10/8) × fOUT)/L) results in a line rate that is ≤12.5 Gbps. fOUT is the output sample rate and is denoted by fS/DCM, where DCM = decimation ratio. 4 Can be controlled by the SPI.
AC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 2. AD9234-500 AD9234-1000 Parameter1 Temperature Min Typ Max Min Typ Max Unit
ANALOG INPUT FULL SCALE Full 1.63 1.34 V p-p NOISE DENSITY2 Full −150 −151 dBFS/Hz SIGNAL-TO-NOISE RATIO (SNR)3 fIN = 10 MHz 25°C 65.9 64.2 dBFS fIN = 170 MHz Full 65.1 65.8 61.6 63.9 dBFS fIN = 340 MHz 25°C 65.6 63.4 dBFS fIN = 450 MHz 25°C 65.3 63.1 dBFS fIN = 737 MHz 25°C 64.2 61.6 dBFS fIN = 985 MHz 25°C 63.6 60.7 dBFS fIN = 1410 MHz 25°C 62.2 58.8 dBFS SNR AND DISTORTION RATIO (SINAD)3 fIN = 10 MHz 25°C 65.8 64.1 dBFS fIN = 170 MHz Full 65.0 65.7 61.2 63.8 dBFS fIN = 340 MHz 25°C 65.5 63.3 dBFS fIN = 450 MHz 25°C 65.2 63.0 dBFS fIN = 737 MHz 25°C 63.7 61.5 dBFS fIN = 985 MHz 25°C 63.1 60.6 dBFS fIN = 1410 MHz 25°C 61.2 58.7 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 10.7 10.4 Bits fIN = 170 MHz Full 10.5 10.6 9.9 10.3 Bits fIN = 340 MHz 25°C 10.6 10.2 Bits fIN = 450 MHz 25°C 10.5 10.2 Bits fIN = 737 MHz 25°C 10.3 9.9 Bits fIN = 985 MHz 25°C 10.2 9.8 Bits fIN = 1410 MHz 25°C 9.9 9.5 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR)3 fIN = 10 MHz 25°C 84 89 dBFS fIN = 170 MHz Full 77 85 70 80 dBFS fIN = 340 MHz 25°C 85 79 dBFS fIN = 450 MHz 25°C 87 80 dBFS fIN = 737 MHz 25°C 75 81 dBFS fIN = 985 MHz 25°C 75 79 dBFS fIN = 1410 MHz 25°C 71 78 dBFS Rev. B | Page 6 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9234-1000 AD9234-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust CLOCK JITTER CONSIDERATIONS POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTER (DDC) DDC GENERAL DESCRIPTION HALF-BAND FILTER DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode at 1 GSPS Example 2: Full Bandwidth Mode at 500 MSPS Example 3: ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYSREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATION TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE