Datasheet AD9234 (Analog Devices) - 7

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Data Sheet AD9234 AD9234-500 AD9234-1000 Parameter1 Temperature Min Typ Max Min Typ Max Unit
WORST HARMONIC, SECOND OR THIRD3 fIN = 10 MHz 25°C −84 −89 dBFS fIN = 170 MHz Full −85 −77 −80 −70 dBFS fIN = 340 MHz 25°C −85 −79 dBFS fIN = 450 MHz 25°C −87 −80 dBFS fIN = 737 MHz 25°C −75 −82 dBFS fIN = 985 MHz 25°C −75 −79 dBFS fIN = 1410 MHz 25°C −71 −78 dBFS WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC3 fIN = 10 MHz 25°C −96 −89 dBFS fIN = 170 MHz Full −82 −95 −85 −76 dBFS fIN = 340 MHz 25°C −94 −83 dBFS fIN = 450 MHz 25°C −93 −82 dBFS fIN = 737 MHz 25°C −88 −81 dBFS fIN = 985 MHz 25°C −89 −85 dBFS fIN = 1410 MHz 25°C −86 −80 dBFS TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7 dBFS fIN1 = 187 MHz, fIN2 = 190 MHz 25°C −90 −81 dBFS fIN1 = 338 MHz, fIN2 = 341 MHz 25°C −86 −78 dBFS CROSSTALK4 25°C 95 95 dB FULL POWER BANDWIDTH5 25°C 2 2 GHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Noise density is measured at a low analog input frequency (30 MHz). 3 See Table 9 for recommended settings for the buffer current setting optimized for SFDR. 4 Crosstalk is measured at 170 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel. 5 Measured with circuit shown in Figure 64. Rev. B | Page 7 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9234-1000 AD9234-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust CLOCK JITTER CONSIDERATIONS POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTER (DDC) DDC GENERAL DESCRIPTION HALF-BAND FILTER DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode at 1 GSPS Example 2: Full Bandwidth Mode at 500 MSPS Example 3: ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYSREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATION TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE