Datasheet AD9674 (Analog Devices) - 2

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AD9674 Data Sheet TABLE OF CONTENTS
Features .. 1 Analog Test Signal Generation ... 31 Applications ... 1 CW Doppler Operation ... 32 General Description ... 1 Digital RF Decimator ... 33 Revision History ... 2 Vector Profile .. 33 Functional Block Diagram .. 3 RF Decimator .. 34 Specifications ... 4 Digital Test Waveforms .. 34 AC Specifications .. 4 Digital block Power Saving scheme ... 35 Digital Specifications ... 7 Serial Port Interface (SPI) .. 36 Switching Specifications .. 8 Hardware Interface ... 36 ADC Timing Diagram ... 9 Memory Map .. 38 CW Doppler Timing Diagram ... 9 Reading the Memory Map Table .. 38 Absolute Maximum Ratings .. 11 Reserved Locations .. 38 Thermal Impedance ... 11 Default Values ... 38 ESD Caution .. 11 Logic Levels ... 38 Pin Configuration and Function Descriptions ... 12 Recommended Start-Up Sequence .. 38 Typical Performance Characteristics ... 15 Memory Map Register Descriptions .. 46 TGC Mode ... 15 Outline Dimensions ... 47 CW Doppler Mode ... 19 Ordering Guide .. 47 Theory of Operation .. 20 TGC Operation ... 20
REVISION HISTORY 1/16—Revision A: Initial Version
Rev. A | Page 2 of 47 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagram CW Doppler Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Digital Outputs and Timing Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation DIGITAL RF DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED START-UP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE