Datasheet AD9674 (Analog Devices) - 3

制造商Analog Devices
描述Octal Ultrasound AFE
页数 / 页47 / 3 — Data Sheet. AD9674. FUNCTIONAL BLOCK DIAGRAM. AVDD1 AVDD2. PDWN STBY. …
修订版A
文件格式/大小PDF / 992 Kb
文件语言英语

Data Sheet. AD9674. FUNCTIONAL BLOCK DIAGRAM. AVDD1 AVDD2. PDWN STBY. DVDD. DRVDD. CWQ+. LO-A TO LO-H. CWD I/Q. CWQ–. DEMODULATOR. CWI+

Data Sheet AD9674 FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 PDWN STBY DVDD DRVDD CWQ+ LO-A TO LO-H CWD I/Q CWQ– DEMODULATOR CWI+

该数据表的模型线

文件文字版本

Data Sheet AD9674 FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 PDWN STBY DVDD DRVDD CWQ+ LO-A TO LO-H CWD I/Q CWQ– DEMODULATOR CWI+ LOSW-A TO LOSW-H CWI– LI-A TO LI-H 14-BIT DOUTA+ TO DOUTH+ FILTER/ LNA VGA SERIALIZER LVDS LG-A TO LG-H AAF ADC DECIMATOR DOUTA– TO DOUTH– AD9674 8 CHANNELS FCO+ SERIAL DATA LO REFERENCE NCO FCO– PORT RATE GENERATION INTERFACE MULTIPLIER DCO+ DCO– + B K O N+ N– EF AS O3 K+ K– IG– IG+ LO+ LO– DI AI AI CS CL S M M VR S CL CL ESET ESET G G RBI TR TR _ _ R R ADDR4 TX TX TO GP O O0
001
GP ADDR0 T
1293- 1 Figure 1. Rev. A | Page 3 of 47 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagram CW Doppler Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Digital Outputs and Timing Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation DIGITAL RF DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED START-UP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE