Datasheet AD9253-EP (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 11 / 6 — AD9253-EP. Enhanced Product. SWITCHING SPECIFICATIONS. Table 4. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 233 Kb |
| 文件语言 | 英语 |
AD9253-EP. Enhanced Product. SWITCHING SPECIFICATIONS. Table 4. Parameter1, 2. Temp. Min. Typ. Max. Unit
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AD9253-EP Enhanced Product SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4. Parameter1, 2 Temp Min Typ Max Unit
CLOCK3 Input Clock Rate Full 10 1000 MHz Conversion Rate4 Full 10 125 MSPS Clock Pulse Width High (tEH) Full 4.00 ns Clock Pulse Width Low (tEL) Full 4.00 ns OUTPUT PARAMETERS3 Propagation Delay (tPD) Full 2.3 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 ns DCO Propagation Delay (tCPD)5 Full tFCO + (tSAMPLE/16) ns DCO-to-Data Delay (tDATA)5 Full (tSAMPLE/16) − 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ps DCO-to-FCO Delay (tFRAME)5 Full (tSAMPLE/16) − 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ps Lane Delay (tLD) 90 ps Data to Data Skew (tDATA-MAX − tDATA-MIN) Full ±50 ±200 ps Wake-Up Time (Standby) 25°C 250 ns Wake-Up Time (Power-Down)6 25°C 375 μs Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay (tA) 25°C 1 ns Aperture Uncertainty (Jitter, tJ) 25°C 135 fs rms Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section of the AD9253 data sheet for the maximum conversion rate in one-lane output mode. 5 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. B | Page 6 of 11 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4. Parameter1, 2 Temp Min Typ Max Unit
CLOCK3 Input Clock Rate Full 10 1000 MHz Conversion Rate4 Full 10 125 MSPS Clock Pulse Width High (tEH) Full 4.00 ns Clock Pulse Width Low (tEL) Full 4.00 ns OUTPUT PARAMETERS3 Propagation Delay (tPD) Full 2.3 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 ns DCO Propagation Delay (tCPD)5 Full tFCO + (tSAMPLE/16) ns DCO-to-Data Delay (tDATA)5 Full (tSAMPLE/16) − 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ps DCO-to-FCO Delay (tFRAME)5 Full (tSAMPLE/16) − 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ps Lane Delay (tLD) 90 ps Data to Data Skew (tDATA-MAX − tDATA-MIN) Full ±50 ±200 ps Wake-Up Time (Standby) 25°C 250 ns Wake-Up Time (Power-Down)6 25°C 375 μs Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay (tA) 25°C 1 ns Aperture Uncertainty (Jitter, tJ) 25°C 135 fs rms Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section of the AD9253 data sheet for the maximum conversion rate in one-lane output mode. 5 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. B | Page 6 of 11 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide