Datasheet AD6641 (Analog Devices) - 6

link to page 28 link to page 28 link to page 6 link to page 7 link to page 7 link to page 7
AD6641 DIGITAL SPECIFICATIONS
AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 3. AD6641-500 Parameter 1 Temp Min Typ Max Unit
CLOCK INPUTS (CLK±) Logic Compliance Full CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage High Level Input (VIH) Full 0.2 1.8 V p-p Low Level Input (VIL) Full −1.8 −0.2 V p-p High Level Input Current (IIH) Full −10 +10 μA Low Level Input Current (IIL) Full −10 +10 μA Input Resistance (Differential) Full 8 10 12 kΩ Input Capacitance Full 4 pF LOGIC INPUTS (SPI, SPORT) Logic Compliance Full CMOS Logic 1 Voltage Full 0.8 × SPI_VDDIO V Logic 0 Voltage Full 0.2 × SPI_VDDIO V Logic 1 Input Current (SDIO) Full 0 μA Logic 0 Input Current (SDIO) Full −60 μA Logic 1 Input Current (SCLK) Full 50 μA Logic 0 Input Current (SCLK) Full 0 μA Input Capacitance 25°C 4 pF LOGIC INPUTS (DUMP, CSB) Logic Compliance Full CMOS Logic 1 Voltage Full 0.8 × DRVDD V Logic 0 Voltage Full 0.2 × DRVDD V Logic 1 Input Current Full 0 μA Logic 0 Input Current Full −60 μA Input Capacitance 25°C 4 pF LOGIC INPUTS (FILL±) Logic Compliance Full CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage High Level Input (VIH) Full 0.2 1.8 V p-p Low Level Input (VIL) Full −1.8 −0.2 V p-p High Level Input Current (IIH) Full −10 +10 μA Low Level Input Current (IIL) Full −10 +10 μA Input Resistance (Differential) Full 8 10 12 kΩ Input Capacitance Full 4 pF LOGIC OUTPUTS2 (FULL, EMPTY) Logic Compliance Full CMOS High Level Output Voltage Full DRVDD − 0.05 V Low Level Output Voltage Full DRGND + 0.05 V LOGIC OUTPUTS2 (SPI, SPORT) Logic Compliance Full CMOS High Level Output Voltage Full SPI_VDDIO − 0.05 V Low Level Output Voltage Full DRGND + 0.05 V Rev. 0 | Page 6 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS SPI REGISTER MAP THEORY OF OPERATION FIFO OPERATION Single Capture Mode Fill Pin Timing Dump Pin Timing SPORT Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High SCLK Signal (5) SDFS Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Parallel Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High PCLK± Signal (5) PD[11:0] Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Continuous Capture Mode FIFO OUTPUT INTERFACES SPORT Interface Serial Data Frame (Serial Bus Master) CMOS Output Interface LVDS Output Interface ANALOG INPUT AND VOLTAGE REFERENCE VREF CONFIGURATION USING THE SPI OUTLINE DIMENSIONS ORDERING GUIDE