Datasheet AD9467-EP (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter |
| 页数 / 页 | 15 / 6 — AD9467-EP. Enhanced Product. DIGITAL SPECIFICATIONS. Table 3. Parameter1. … |
| 文件格式/大小 | PDF / 612 Kb |
| 文件语言 | 英语 |
AD9467-EP. Enhanced Product. DIGITAL SPECIFICATIONS. Table 3. Parameter1. Temp. Min. Typ. Max. Unit
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AD9467-EP Enhanced Product DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.
Table 3. Parameter1 Temp Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 mV p-p Input Common-Mode Voltage Full 0.8 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 2.5 pF LOGIC INPUTS (SCLK, CSB, SDIO) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF LOGIC OUTPUT (SDIO)3 Logic 1 Voltage (IOH = 800 µA) Full 1.7/3.1 V Logic 0 Voltage (IOL = 50 µA) Full 0.3 V DIGITAL OUTPUTS (D0+ to D15+, D0− to D15−, DCO+, DCO−, OR+, OR−) Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 545 mV Output Offset Voltage (VOS) Full 1.125 1.375 V Output Coding (Default) Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This depends on if SPIVDD is tied to a 1.8 V or 3.3 V supply. Rev. 0 | Page 6 of 15 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.
Table 3. Parameter1 Temp Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 mV p-p Input Common-Mode Voltage Full 0.8 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 2.5 pF LOGIC INPUTS (SCLK, CSB, SDIO) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF LOGIC OUTPUT (SDIO)3 Logic 1 Voltage (IOH = 800 µA) Full 1.7/3.1 V Logic 0 Voltage (IOL = 50 µA) Full 0.3 V DIGITAL OUTPUTS (D0+ to D15+, D0− to D15−, DCO+, DCO−, OR+, OR−) Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 545 mV Output Offset Voltage (VOS) Full 1.125 1.375 V Output Coding (Default) Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This depends on if SPIVDD is tied to a 1.8 V or 3.3 V supply. Rev. 0 | Page 6 of 15 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE