Datasheet AD9650-EP (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| 页数 / 页 | 12 / 3 — Data Sheet. AD9650-EP. SPECIFICATIONS ADC DC SPECIFICATIONS. Table 1. … |
| 文件格式/大小 | PDF / 252 Kb |
| 文件语言 | 英语 |
Data Sheet. AD9650-EP. SPECIFICATIONS ADC DC SPECIFICATIONS. Table 1. Parameter. Temperature. Min. Typ. Max. Unit
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Data Sheet AD9650-EP SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled, unless otherwise noted.
Table 1. Parameter Temperature Min Typ Max Unit
RESOLUTION Full 16 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±0.4 ±0.7 % FSR Gain Error Full ±0.4 ±2.5 % FSR Differential Nonlinearity (DNL)1 Full −1 +1.3 LSB 25°C ±0.7 LSB Integral Nonlinearity (INL)1 Full ±6 LSB 25°C ±3 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.1 ±0.4 % FSR Gain Error Full ±0.5 ±1.3 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±15 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1.35 V Mode) Full ±7 ±14 mV Load Regulation at 1.0 mA Full 10 mV INPUT REFERRED NOISE VREF = 1.35 V 25°C 1.5 LSB rms ANALOG INPUT Input Span, VREF = 1.35 V Full 2.7 V p-p Input Capacitance2 Full 11 pF Input Common-Mode Voltage Full 0.9 V REFERENCE INPUT RESISTANCE Full 6 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current1 IAVDD Full 332 340 mA IDRVDD (1.8 V CMOS) Full 36 mA IDRVDD (1.8 V LVDS) Full 100 mA POWER CONSUMPTION DC Input Full 656 675 mW Sine Wave Input1 (DRVDD = 1.8 V) CMOS Output Mode Full 663 mW LVDS Output Mode Full 778 mW Standby Power3 Full 50 mW Power-Down Power Full 0.25 2.5 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK+ and CLK− pins inactive (set to AVDD or AGND). Rev. 0 | Page 3 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide
Data Sheet AD9650-EP SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled, unless otherwise noted.
Table 1. Parameter Temperature Min Typ Max Unit
RESOLUTION Full 16 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±0.4 ±0.7 % FSR Gain Error Full ±0.4 ±2.5 % FSR Differential Nonlinearity (DNL)1 Full −1 +1.3 LSB 25°C ±0.7 LSB Integral Nonlinearity (INL)1 Full ±6 LSB 25°C ±3 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.1 ±0.4 % FSR Gain Error Full ±0.5 ±1.3 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±15 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1.35 V Mode) Full ±7 ±14 mV Load Regulation at 1.0 mA Full 10 mV INPUT REFERRED NOISE VREF = 1.35 V 25°C 1.5 LSB rms ANALOG INPUT Input Span, VREF = 1.35 V Full 2.7 V p-p Input Capacitance2 Full 11 pF Input Common-Mode Voltage Full 0.9 V REFERENCE INPUT RESISTANCE Full 6 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current1 IAVDD Full 332 340 mA IDRVDD (1.8 V CMOS) Full 36 mA IDRVDD (1.8 V LVDS) Full 100 mA POWER CONSUMPTION DC Input Full 656 675 mW Sine Wave Input1 (DRVDD = 1.8 V) CMOS Output Mode Full 663 mW LVDS Output Mode Full 778 mW Standby Power3 Full 50 mW Power-Down Power Full 0.25 2.5 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK+ and CLK− pins inactive (set to AVDD or AGND). Rev. 0 | Page 3 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide