Datasheet AD9650-EP (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| 页数 / 页 | 12 / 8 — AD9650-EP. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL … |
| 文件格式/大小 | PDF / 252 Kb |
| 文件语言 | 英语 |
AD9650-EP. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS. Parameter. Rating. Table 7. Thermal Resistance
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AD9650-EP Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS Parameter Rating
The exposed pad on the underside of the TQFP package must Electrical1 be soldered to the ground plane for the package. Soldering the AVDD to AGND −0.3 V to +2.0 V exposed pad to the PCB increases the reliability of the solder DRVDD to AGND −0.3 V to +2.0 V joints and maximizes the thermal capability of the package. VIN+A/VIN+B, VIN−A/VIN−B −0.3 V to AVDD + 0.2 V Typical θJA is specified for a 4-layer PCB with a solid ground to AGND plane. Airflow improves heat dissipation, which reduces θJA. In CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V addition, metal in direct contact with the package leads from metal SYNC to AGND −0.3 V to AVDD + 0.2 V traces, through holes, ground, and power planes reduces θJA. VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V
Table 7. Thermal Resistance
VCM to AGND −0.3 V to AVDD + 0.2 V
Airflow
RBIAS to AGND −0.3 V to AVDD + 0.2 V
Package Type Velocity (m/sec) θ 1, 2, 4 1, 3, 4 JA θJC Unit
CSB to AGND −0.3 V to DRVDD + 0.2 V 80-Lead TQFP_EP 0 22.48 4.67 °C/W SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V 1 Per JEDEC JESD51-7, plus JEDEC JESD25-5 2S2P test board. SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 OEB −0.3 V to DRVDD + 0.2 V Per MIL-STD-883, Method 1012.1. 4 Per JEDEC STD, a 7 × 7 via array should be used to achieve this value. PDWN −0.3 V to DRVDD + 0.2 V D0+/D0− Through D15+/D15− −0.3 V to DRVDD + 0.2 V
ESD CAUTION
to AGND DCO+/DCO− to AGND −0.3 V to DRVDD + 0.2 V Environmental Operating Temperature Range −55°C to +85°C (Ambient) Maximum Junction Temperature 150°C Under Bias Storage Temperature Range −65°C to +150°C (Ambient) 1 The inputs and outputs are rated to the supply voltage (AVDD + 0.2 V or DRVDD + 0.2 V), but they should not exceed 2.1 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide
AD9650-EP Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS Parameter Rating
The exposed pad on the underside of the TQFP package must Electrical1 be soldered to the ground plane for the package. Soldering the AVDD to AGND −0.3 V to +2.0 V exposed pad to the PCB increases the reliability of the solder DRVDD to AGND −0.3 V to +2.0 V joints and maximizes the thermal capability of the package. VIN+A/VIN+B, VIN−A/VIN−B −0.3 V to AVDD + 0.2 V Typical θJA is specified for a 4-layer PCB with a solid ground to AGND plane. Airflow improves heat dissipation, which reduces θJA. In CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V addition, metal in direct contact with the package leads from metal SYNC to AGND −0.3 V to AVDD + 0.2 V traces, through holes, ground, and power planes reduces θJA. VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V
Table 7. Thermal Resistance
VCM to AGND −0.3 V to AVDD + 0.2 V
Airflow
RBIAS to AGND −0.3 V to AVDD + 0.2 V
Package Type Velocity (m/sec) θ 1, 2, 4 1, 3, 4 JA θJC Unit
CSB to AGND −0.3 V to DRVDD + 0.2 V 80-Lead TQFP_EP 0 22.48 4.67 °C/W SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V 1 Per JEDEC JESD51-7, plus JEDEC JESD25-5 2S2P test board. SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 OEB −0.3 V to DRVDD + 0.2 V Per MIL-STD-883, Method 1012.1. 4 Per JEDEC STD, a 7 × 7 via array should be used to achieve this value. PDWN −0.3 V to DRVDD + 0.2 V D0+/D0− Through D15+/D15− −0.3 V to DRVDD + 0.2 V
ESD CAUTION
to AGND DCO+/DCO− to AGND −0.3 V to DRVDD + 0.2 V Environmental Operating Temperature Range −55°C to +85°C (Ambient) Maximum Junction Temperature 150°C Under Bias Storage Temperature Range −65°C to +150°C (Ambient) 1 The inputs and outputs are rated to the supply voltage (AVDD + 0.2 V or DRVDD + 0.2 V), but they should not exceed 2.1 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide