Datasheet AD9650-EP (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| 页数 / 页 | 12 / 7 — Data Sheet. AD9650-EP. Timing Diagrams. N – 1. N + 4. N + 5. N + 3. VIN. … |
| 文件格式/大小 | PDF / 252 Kb |
| 文件语言 | 英语 |
Data Sheet. AD9650-EP. Timing Diagrams. N – 1. N + 4. N + 5. N + 3. VIN. N + 1. N + 2. tCH. tCLK. CLK+. CLK–. tDCO. DCOA/DCOB. tSKEW. CH A/CH B DATA
该数据表的模型线
文件文字版本
Data Sheet AD9650-EP Timing Diagrams N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW CH A/CH B DATA N – 13 N – 12 N – 11 N – 10 N – 9 N – 8
002
tPD
1312- 1 Figure 2. CMOS Default Output Mode Data Output Timing
N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW tPD
003
CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A/CH B DATA N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8
1312- 1 Figure 3. CMOS Interleaved Output Mode Data Output Timing
N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCO+/DCO– tSKEW tPD
004
CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A/CH B DATA N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8
1312- 1 Figure 4. LVDS Mode Data Output Timing
CLK+ t t SSYNC HSYNC SYNC
005 1312- 1 Figure 5. SYNC Input Timing Requirements Rev. 0 | Page 7 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide
002
tPD
1312- 1 Figure 2. CMOS Default Output Mode Data Output Timing
N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW tPD
003
CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A/CH B DATA N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8
1312- 1 Figure 3. CMOS Interleaved Output Mode Data Output Timing
N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCO+/DCO– tSKEW tPD
004
CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A/CH B DATA N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8
1312- 1 Figure 4. LVDS Mode Data Output Timing
CLK+ t t SSYNC HSYNC SYNC
005 1312- 1 Figure 5. SYNC Input Timing Requirements Rev. 0 | Page 7 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide