Datasheet AD9650-EP (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| 页数 / 页 | 12 / 6 — AD9650-EP. Data Sheet. SWITCHING SPECIFICATIONS. Table 4. Parameter. … |
| 文件格式/大小 | PDF / 252 Kb |
| 文件语言 | 英语 |
AD9650-EP. Data Sheet. SWITCHING SPECIFICATIONS. Table 4. Parameter. Temperature. Min. Typ. Max. Unit. TIMING SPECIFICATIONS
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AD9650-EP Data Sheet SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS enabled, unless otherwise noted.
Table 4. Parameter Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 640 MHz Conversion Rate1 DCS Enabled Full 20 105 MSPS DCS Disabled Full 10 105 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 9.5 ns CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Full 2.85 4.75 6.65 ns Divide-by-1 Mode, DCS Disabled Full 4.5 4.75 5.0 ns Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 ns Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.075 ps rms DATA OUTPUT PARAMETERS CMOS Mode Data Propagation Delay (tPD) Full 2.8 3.5 4.2 ns DCO Propagation Delay (tDCO)2 Full 3.1 ns DCO to Data Skew (tSKEW) Full −0.6 −0.4 0 ns LVDS Mode Data Propagation Delay (tPD) Full 2.9 3.7 4.5 ns DCO Propagation Delay (tDCO)2 Full 3.9 ns DCO to Data Skew (tSKEW) Full −0.1 +0.2 +0.5 ns CMOS Mode Pipeline Delay (Latency) Full 12 Cycles LVDS Mode Pipeline Delay (Latency), Channel A/Channel B Full 12/12.5 Cycles Wake-Up Time3 Full 500 µs Out-of-Range Recovery Time Full 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17. 3 Wake-up time is defined as the time required to return to normal operation from power-down mode.
TIMING SPECIFICATIONS Table 5. Parameter Description Limit Unit
SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.3 ns typ tHSYNC SYNC to rising edge of CLK+ hold time 0.4 ns typ SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to 10 ns min an output relative to the SCLK falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output to 10 ns min an input relative to the SCLK rising edge Rev. 0 | Page 6 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide
AD9650-EP Data Sheet SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS enabled, unless otherwise noted.
Table 4. Parameter Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 640 MHz Conversion Rate1 DCS Enabled Full 20 105 MSPS DCS Disabled Full 10 105 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 9.5 ns CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Full 2.85 4.75 6.65 ns Divide-by-1 Mode, DCS Disabled Full 4.5 4.75 5.0 ns Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 ns Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.075 ps rms DATA OUTPUT PARAMETERS CMOS Mode Data Propagation Delay (tPD) Full 2.8 3.5 4.2 ns DCO Propagation Delay (tDCO)2 Full 3.1 ns DCO to Data Skew (tSKEW) Full −0.6 −0.4 0 ns LVDS Mode Data Propagation Delay (tPD) Full 2.9 3.7 4.5 ns DCO Propagation Delay (tDCO)2 Full 3.9 ns DCO to Data Skew (tSKEW) Full −0.1 +0.2 +0.5 ns CMOS Mode Pipeline Delay (Latency) Full 12 Cycles LVDS Mode Pipeline Delay (Latency), Channel A/Channel B Full 12/12.5 Cycles Wake-Up Time3 Full 500 µs Out-of-Range Recovery Time Full 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17. 3 Wake-up time is defined as the time required to return to normal operation from power-down mode.
TIMING SPECIFICATIONS Table 5. Parameter Description Limit Unit
SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.3 ns typ tHSYNC SYNC to rising edge of CLK+ hold time 0.4 ns typ SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to 10 ns min an output relative to the SCLK falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output to 10 ns min an input relative to the SCLK rising edge Rev. 0 | Page 6 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide