Datasheet AD9273 (Analog Devices) - 6

AD9273 AD9273-25 AD9273-40 AD9273-50 Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
GAIN ACCURACY 25°C Gain Law Confor- 0 V < GAIN+ 1.5 1.5 1.5 dB mance Error < 0.16 V 0.16 V < GAIN+ −1.6 +1.6 −1.6 +1.6 −1.7 +1.7 dB < 1.44 V 1.44 V < GAIN+ −2.5 −2.5 −2.5 dB < 1.6 V Linear Gain Error GAIN+ = 0.8 V, −1.6 +1.6 −1.6 +1.6 −1.7 +1.7 dB normalized for ideal AAF loss Channel-to-Channel 0.16 V < GAIN+ 0.1 0.1 0.1 dB Matching < 1.44 V GAIN CONTROL INTERFACE Normal Operating 0 1.6 0 1.6 0 1.6 V Range Gain Range GAIN+ = 42 42 42 dB 0 V to 1.6 V Scale Factor 28 28 28 dB/V Response Time 42 dB change 750 750 750 ns Gain+ Impedance Single ended 10 10 10 MΩ Gain− Impedance Single ended 70 70 70 kΩ CW DOPPLER MODE Transconductance Differential, 5.4/7.3/10.9 5.4/7.3/10.9 5.4/7.3/10.9 mA/V LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB Output Level Range Differential, 1.5 3.6 1.5 3.6 1.5 3.6 V CW Doppler output pins Input-Referred LNA gain = 2.6/2.1/1.6 2.6/2.1/1.6 2.6/2.1/1.6 nV/√Hz Noise Voltage 15.6 dB/ 17.9 dB/ 21.3 dB, RS = 0 Ω, RFB = ∞, RL = 675 Ω Input-Referred LNA gain = 160/159/158 160/159/158 160/159/158 dBFS/√Hz Dynamic Range 15.6 dB/ 17.9 dB/ 21.3 dB, RS = 0 Ω, RFB = ∞ Two-Tone IMD3 fIN1 = 5.0 MHz at −70 −70 −70 dBc (2 × F1 − F2) −1 dBFS (FS at Distortion LNA input), fIN2 = 5.01 MHz at −21 dBFS (FS at LNA input), LNA gain = 21.3 dB Output DC Bias Single ended, 2.4 2.4 2.4 mA per channel Maximum Output Single ended, ±2 ±2 ±2 mA p-p Swing per channel POWER SUPPLY AVDD1 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V AVDD2 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IAVDD1 Full-channel 158 186 223 mA mode CW Doppler 32 32 32 mA mode with four channels enabled Rev. B | Page 6 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE Caution RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE