Datasheet AD9273 (Analog Devices) - 7

AD9273 AD9273-25 AD9273-40 AD9273-50 Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
IAVDD2 Full-channel 150 150 150 mA mode CW Doppler 70 70 70 mA mode with four channels enabled IDRVDD 47 49 50 mA Total Power Includes output 819 940 873 996 943 1072 mW Dissipation drivers, full- channel mode, no signal CW Doppler 275 275 275 mW mode with four channels enabled Power-Down 5 5 5 mW Dissipation Standby Power 148 158 170 mW Dissipation Power Supply 1.6 1.6 1.6 mV/V Rejection Ratio (PSRR) ADC RESOLUTION 12 12 12 Bits ADC REFERENCE Output Voltage Error VREF = 1 V ±20 ±20 ±20 mV Load Regulation At 1.0 mA, 2 2 2 mV VREF = 1 V Input Resistance 6 6 6 kΩ 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 SE = single ended. 3 AAF settings < 5 MHz are out of range and are not supported. 4 The overrange condition is specified as being 6 dB more than the full-scale input range. Rev. B | Page 7 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE Caution RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE