Datasheet AD9272 (Analog Devices)

Octal LNA/VGA/AAF/ADC and Crosspoint Switch AD9272 FEATURES FUNCTIONAL BLOCK DIAGRAM 8 channels of LNA, VGA, AAF, and ADC N Y DD DD1 DD2 B V Low noise preamplifier (LNA) AV AV PDW ST DR Input-referred noise voltage = 0.75 nV/√Hz LOSW-A AD9272 (gain = 21.3 dB) @ 5 MHz typical LO-A SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB LI-A 12-BIT DOUTA+ LNA SERIAL VGA Single-ended input; V LG-A ADC LVDS DOUTA– IN maximum = 733 mV p-p/ AAF LOSW-B 550 mV p-p/367 mV p-p LO-B Dual-mode active input impedance matching LI-B 12-BIT DOUTB+ LNA SERIAL VGA Bandwidth (BW) > 100 MHz LG-B ADC LVDS DOUTB– AAF Full-scale (FS) output = 4.4 V p-p differential LOSW-C LO-C Variable gain amplifier (VGA) LI-C 12-BIT SERIAL DOUTC+ Attenuator range = −42 dB to 0 dB LNA VGA LG-C ADC LVDS DOUTC– AAF SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB LOSW-D Linear-in-dB gain control LO-D LI-D 12-BIT VGA SERIAL DOUTD+ Antialiasing filter (AAF) LNA LG-D ADC LVDS DOUTD– AAF Programmable 2nd-order low-pass filter (LPF) from LOSW-E 8 MHz to 18 MHz LO-E LI-E DOUTE+ Programmable high-pass filter (HPF) 12-BIT LNA SERIAL VGA LG-E ADC LVDS DOUTE– Analog-to-digital converter (ADC) AAF LOSW-F 12 bits at 10 MSPS to 80 MSPS LO-F SNR = 70 dB LI-F 12-BIT DOUTF+ LNA SERIAL LG-F VGA ADC LVDS DOUTF– SFDR = 75 dB AAF LOSW-G Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) LO-G Data and frame clock outputs LI-G 12-BIT DOUTG+ LNA SERIAL VGA LG-G ADC LVDS DOUTG– Includes an 8 × 8 differential crosspoint switch to support AAF LOSW-H continuous wave (CW) Doppler LO-H Low power, 195 mW per channel at 12 bits/40 MSPS (TGC) LI-H 12-BIT DOUTH+ LNA SERIAL VGA ADC 120 mW per channel in CW Doppler LG-H LVDS DOUTH– AAF Flexible power-down modes R L Overload recovery in <10 ns A T A E LIE FCO+ R ACE T RF IP FCO– Fast recovery from low power standby mode, <2 μs SERI PO E DAT RA LT REFERENCE U DCO+ 100-lead TQFP INT SWITCH M DCO– ARRAY APPLICATIONS + + – F B K O – Medical imaging/ultrasound 0] 0]– E IN IN AS L K+ K AND CS 7: 7: VR SDI SC CL CL Automotive radar GA GA RBI D[ D[
01 0 9-
CW CW
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GENERAL DESCRIPTION
07 Figure 1. The AD9272 is designed for low cost, low power, small size, and The LNA has a single-ended-to-differential gain that is selectable ease of use. It contains eight channels of a low noise preamplifier through the SPI. The LNA input-referred noise voltage is typically (LNA) with a variable gain amplifier (VGA), an antialiasing 0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred filter (AAF), and a 12-bit, 10 MSPS to 80 MSPS analog-to- noise voltage of the entire channel is 0.85 nV/√Hz at maximum digital converter (ADC). gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB Each channel features a variable gain range of 42 dB, a fully LNA gain, the input SNR is about 92 dB. In CW Doppler mode, differential signal path, an active input preamplifier termination, a the LNA output drives a transconductance amp that is switched maximum gain of up to 52 dB, and an ADC with a conversion through an 8 × 8 differential crosspoint switch. The switch is rate of up to 80 MSPS. The channel is optimized for dynamic programmable through the SPI. performance and low power in applications where a small package size is critical.
Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE Caution RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE