Datasheet AD9272 (Analog Devices) - 3

AD9272
The AD9272 requires a LVPECL-/CMOS-/LVDS-compatible Fabricated in an advanced CMOS process, the AD9272 is sample rate clock for full performance operation. No external available in a 16 mm × 16 mm, RoHS-compliant, 100-lead reference or driver components are required for many TQFP. It is specified over the industrial temperature range of applications. −40°C to +85°C. The ADC automatically multiplies the sample rate clock for
PRODUCT HIGHLIGHTS
the appropriate LVDS serial data rate. A data clock (DCO±) for 1. Small Footprint. Eight channels are contained in a capturing data on the output and a frame clock (FCO±) trigger small, space-saving package. A full TGC path, ADC, and for signaling a new output byte are provided. crosspoint switch are contained within a 100-lead, 16 mm × Powering down individual channels is supported to increase 16 mm TQFP. battery life for portable applications. There is also a standby 2. Low Power of 195 mW Per Channel at 40 MSPS. mode option that allows quick power-up for power cycling. In 3. Integrated Crosspoint Switch. This switch allows numerous CW Doppler operation, the VGA, antialiasing filter (AAF), and multichannel configuration options to enable the CW ADC are powered down. The power of the time gain control Doppler mode. (TGC) path scales with selectable speed grades. 4. Ease of Use. A data clock output (DCO±) operates up to The ADC contains several features designed to maximize flexibility 480 MHz and supports double data rate (DDR) operation. and minimize system cost, such as a programmable clock, data 5. User Flexibility. Serial port interface (SPI) control offers a wide alignment, and programmable digital test pattern generation. The range of flexible features to meet specific system requirements. digital test patterns include built-in fixed patterns, built-in 6. Integrated Second-Order Antialiasing Filter. This filter is pseudorandom patterns, and custom user-defined test patterns placed between the VGA and the ADC and is programmable entered via the serial port interface. from 8 MHz to 18 MHz. Rev. C | Page 3 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE Caution RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE