Datasheet AD9272 (Analog Devices) - 7

制造商Analog Devices
描述Octal LNA/VGA/AAF/ADC and Crosspoint Switch
页数 / 页44 / 7 — AD9272. AD9272-40 AD9272-65 AD9272-80. Parameter1. Conditions. Min. Typ …
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AD9272. AD9272-40 AD9272-65 AD9272-80. Parameter1. Conditions. Min. Typ Max. Unit

AD9272 AD9272-40 AD9272-65 AD9272-80 Parameter1 Conditions Min Typ Max Unit

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AD9272 AD9272-40 AD9272-65 AD9272-80 Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
IAVDD1 Full-channel 210 280 335 mA mode CW Doppler mode 32 32 32 mA with four channels enabled IAVDD2 Full-channel mode 365 365 365 mA CW Doppler mode 140 140 140 mA with four channels enabled IDRVDD 49 51 52 mA Total Power Includes output 1560 1713 1690 1860 1780 1975 mW Dissipation drivers, full- channel mode, no signal CW Doppler mode 475 475 475 mW with four channels enabled Power-Down 5 5 5 mW Dissipation Standby Power 175 200 210 mW Dissipation Power Supply 1.6 1.6 1.6 mV/V Rejection Ratio (PSRR) ADC RESOLUTION 12 12 12 Bits ADC REFERENCE Output Voltage Error VREF = 1 V ±20 ±20 ±20 mV Load Regulation At 1.0 mA, 2 2 2 mV VREF = 1 V Input Resistance 6 6 6 kΩ 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 SE = single-ended. 3 AAF settings < 5 MHz are out of range and not supported. 4 The overrange condition is specified as being 6 dB more than the full-scale input range. Rev. C | Page 7 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE Caution RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE