Datasheet HMC625BLP5E (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 0.5 dB LSB GaAs MMIC 6-Bit Digital Variable Gain Amplifier, DC - 5 GHz |
| 页数 / 页 | 9 / 4 — HMC625BLP5E. 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL. VARIABLE GAIN AMPLIFIER, … |
| 文件格式/大小 | PDF / 692 Kb |
| 文件语言 | 英语 |
HMC625BLP5E. 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL. VARIABLE GAIN AMPLIFIER, DC - 5 GHz. Serial Control Interface
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HMC625BLP5E
v02.0616
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 5 GHz Serial Control Interface
The HMC625BLP5E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). It is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, T 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data M transition during output loading. When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and serial input register is loaded L - S asynchronously with paral el digital inputs (D0-D5). When LE is high, 6-bit paral el data is transferred to the attenuator. For all modes of operations, the DVGA state will stay constant while LE is kept low. ITA IG S - D R IE LIF P M IN A A LE G Parameter Typ. B Min. serial period, t 100 ns
Timing Diagram (Latched Parallel Mode)
SCK IA Control set-up time, t 20 ns CS R Control hold-time, t 20 ns CH A LE setup-time, t 10 ns LN V Min. LE pulse width, t 10 ns LEW Min LE pulse spacing, t 630 ns LES Serial clock hold-time from LE, t 10 ns CKN Hold Time t 0 ns PH Latch Enable Minimum width, t 10 ns LEN Setup Time, t 2 ns PS
Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note:
The paral el mode is enabled when P/S is set to low.
Direct Parallel Mode
- The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable) must be at a logic high to control the attenuator in this manner.
Latched Parallel Mode
- The attenuation state is selected using the Control Voltage Inputs and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 781-329-4700 • Order online at www.analog.com Application Support: Phone: 1-800-ANALOG-D
4
Document Outline Typical Applications Features Functional Diagram General Description Electrical Specifications Typical Performance Characteristics Maximum Gain vs. Frequency Normalized Attenuation [2 Input Return Loss [2] Output Return Loss [2] Bit Error vs. Frequency [2] Bit Error vs. Attenuation State [2] Normal Relative Phase vs. Frequency [2] Step Error vs. Frequency [2] Serial Control Interface Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Power-Up States PUP Truth Table Power-On Sequence Absolute Maximum Ratings Truth Table Bookmark 24 Bias Voltage Outline Drawing Package Information Pin Descriptions Application Circuit Evaluation PCB List of Materials for Evaluation PCB 116960 - HMC625ALP5 [1]
v02.0616
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 5 GHz Serial Control Interface
The HMC625BLP5E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). It is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, T 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data M transition during output loading. When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and serial input register is loaded L - S asynchronously with paral el digital inputs (D0-D5). When LE is high, 6-bit paral el data is transferred to the attenuator. For all modes of operations, the DVGA state will stay constant while LE is kept low. ITA IG S - D R IE LIF P M IN A A LE G Parameter Typ. B Min. serial period, t 100 ns
Timing Diagram (Latched Parallel Mode)
SCK IA Control set-up time, t 20 ns CS R Control hold-time, t 20 ns CH A LE setup-time, t 10 ns LN V Min. LE pulse width, t 10 ns LEW Min LE pulse spacing, t 630 ns LES Serial clock hold-time from LE, t 10 ns CKN Hold Time t 0 ns PH Latch Enable Minimum width, t 10 ns LEN Setup Time, t 2 ns PS
Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note:
The paral el mode is enabled when P/S is set to low.
Direct Parallel Mode
- The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable) must be at a logic high to control the attenuator in this manner.
Latched Parallel Mode
- The attenuation state is selected using the Control Voltage Inputs and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 781-329-4700 • Order online at www.analog.com Application Support: Phone: 1-800-ANALOG-D
4
Document Outline Typical Applications Features Functional Diagram General Description Electrical Specifications Typical Performance Characteristics Maximum Gain vs. Frequency Normalized Attenuation [2 Input Return Loss [2] Output Return Loss [2] Bit Error vs. Frequency [2] Bit Error vs. Attenuation State [2] Normal Relative Phase vs. Frequency [2] Step Error vs. Frequency [2] Serial Control Interface Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Power-Up States PUP Truth Table Power-On Sequence Absolute Maximum Ratings Truth Table Bookmark 24 Bias Voltage Outline Drawing Package Information Pin Descriptions Application Circuit Evaluation PCB List of Materials for Evaluation PCB 116960 - HMC625ALP5 [1]