Datasheet HMC625BLP5E (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 0.5 dB LSB GaAs MMIC 6-Bit Digital Variable Gain Amplifier, DC - 5 GHz |
| 页数 / 页 | 9 / 5 — HMC625BLP5E. 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL. VARIABLE GAIN AMPLIFIER, … |
| 文件格式/大小 | PDF / 692 Kb |
| 文件语言 | 英语 |
HMC625BLP5E. 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL. VARIABLE GAIN AMPLIFIER, DC - 5 GHz. Power-Up States. PUP Truth Table
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HMC625BLP5E
v02.0616
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 5 GHz Power-Up States PUP Truth Table
If LE is set to logic LOW at power-up, the logic state of Gain Relative to Maximum T PUP1 and PUP2 determines the power-up state of the LE PUP1 PUP2 Gain M part per PUP truth table. If the LE is set to logic HIGH 0 0 0 -31.5 at power-up, the logic state of D0-D5 determines the 0 1 0 -24 power-up state of the part per truth table. The DVGA 0 0 1 -16 L - S latches in the desired power-up state approximately 0 1 1 Insertion Loss 200 ms after power-up. 1 X X 0 to -31.5 dB ITA Note: The logic state of D0 - D5 determines the
Power-On Sequence
IG power-up state per truth table shown below when LE The ideal power-up sequence is: GND, Vdd, digital is high at power-up. inputs, RF inputs. The relative order of the digital inputs are not important as long as they are powered S - D after Vdd / GND R IE
Absolute Maximum Ratings Truth Table
LIF RF Input Power [1] 11.5 dBm (T = +85 °C) Control Voltage Input Gain Relative to P Digital Inputs (Reset, Shift Clock, -0.5 to Vdd +0.5V Maximum Latch Enable & Serial Input) D5 D4 D3 D2 D1 D0 M Gain Bias Voltage (Vdd) 5.6V High High High High High High 0 dB Collector Bias Voltage (Vcc) 5.5V High High High High High Low -0.5 dB IN A Channel Temperature 150 °C High High High High Low High -1 dB A Continuous Pdiss (T = 85 °C) 0.546 W High High High Low High High -2 dB (derate 8.4 mW/°C above 85 °C) [2] High High Low High High High -4 dB Thermal Resistance [3] 119 °C/W High Low High High High High -8 dB Storage Temperature -65 to +150 °C LE G Low High High High High High -16 dB Operating Temperature -40 to +85 °C B Low Low Low Low Low Low -31.5 dB ESD Sensitivity (HBM) Class 1A IA Any combination of the above states will provide a reduction in [1] The maximum RF input power increases by the same amount R gain approximately equal to the sum of the bits selected. the gain is reduced. The maximum input power at any state is no A more than 28 dBm. V [2] This value is the total power dissipation in the amplifier.
Control Voltage Table
[3] This is the thermal resistance for the amplifier. State Vdd = +3V Vdd = +5V Low 0 to 0.5V @ <1 µA 0 to 0.8V @ <1 µA High 2 to 3V @ <1 µA 2 to 5V @ <1 µA
Bias Voltage
ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS Vdd (V) Idd (Typ.) (mA) 5V 2.5 Vs (V) Is (Typ.) (mA) 5V 85 For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 781-329-4700 • Order online at www.analog.com
5
Application Support: Phone: 1-800-ANALOG-D Document Outline Typical Applications Features Functional Diagram General Description Electrical Specifications Typical Performance Characteristics Maximum Gain vs. Frequency Normalized Attenuation [2 Input Return Loss [2] Output Return Loss [2] Bit Error vs. Frequency [2] Bit Error vs. Attenuation State [2] Normal Relative Phase vs. Frequency [2] Step Error vs. Frequency [2] Serial Control Interface Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Power-Up States PUP Truth Table Power-On Sequence Absolute Maximum Ratings Truth Table Bookmark 24 Bias Voltage Outline Drawing Package Information Pin Descriptions Application Circuit Evaluation PCB List of Materials for Evaluation PCB 116960 - HMC625ALP5 [1]
v02.0616
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 5 GHz Power-Up States PUP Truth Table
If LE is set to logic LOW at power-up, the logic state of Gain Relative to Maximum T PUP1 and PUP2 determines the power-up state of the LE PUP1 PUP2 Gain M part per PUP truth table. If the LE is set to logic HIGH 0 0 0 -31.5 at power-up, the logic state of D0-D5 determines the 0 1 0 -24 power-up state of the part per truth table. The DVGA 0 0 1 -16 L - S latches in the desired power-up state approximately 0 1 1 Insertion Loss 200 ms after power-up. 1 X X 0 to -31.5 dB ITA Note: The logic state of D0 - D5 determines the
Power-On Sequence
IG power-up state per truth table shown below when LE The ideal power-up sequence is: GND, Vdd, digital is high at power-up. inputs, RF inputs. The relative order of the digital inputs are not important as long as they are powered S - D after Vdd / GND R IE
Absolute Maximum Ratings Truth Table
LIF RF Input Power [1] 11.5 dBm (T = +85 °C) Control Voltage Input Gain Relative to P Digital Inputs (Reset, Shift Clock, -0.5 to Vdd +0.5V Maximum Latch Enable & Serial Input) D5 D4 D3 D2 D1 D0 M Gain Bias Voltage (Vdd) 5.6V High High High High High High 0 dB Collector Bias Voltage (Vcc) 5.5V High High High High High Low -0.5 dB IN A Channel Temperature 150 °C High High High High Low High -1 dB A Continuous Pdiss (T = 85 °C) 0.546 W High High High Low High High -2 dB (derate 8.4 mW/°C above 85 °C) [2] High High Low High High High -4 dB Thermal Resistance [3] 119 °C/W High Low High High High High -8 dB Storage Temperature -65 to +150 °C LE G Low High High High High High -16 dB Operating Temperature -40 to +85 °C B Low Low Low Low Low Low -31.5 dB ESD Sensitivity (HBM) Class 1A IA Any combination of the above states will provide a reduction in [1] The maximum RF input power increases by the same amount R gain approximately equal to the sum of the bits selected. the gain is reduced. The maximum input power at any state is no A more than 28 dBm. V [2] This value is the total power dissipation in the amplifier.
Control Voltage Table
[3] This is the thermal resistance for the amplifier. State Vdd = +3V Vdd = +5V Low 0 to 0.5V @ <1 µA 0 to 0.8V @ <1 µA High 2 to 3V @ <1 µA 2 to 5V @ <1 µA
Bias Voltage
ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS Vdd (V) Idd (Typ.) (mA) 5V 2.5 Vs (V) Is (Typ.) (mA) 5V 85 For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 781-329-4700 • Order online at www.analog.com
5
Application Support: Phone: 1-800-ANALOG-D Document Outline Typical Applications Features Functional Diagram General Description Electrical Specifications Typical Performance Characteristics Maximum Gain vs. Frequency Normalized Attenuation [2 Input Return Loss [2] Output Return Loss [2] Bit Error vs. Frequency [2] Bit Error vs. Attenuation State [2] Normal Relative Phase vs. Frequency [2] Step Error vs. Frequency [2] Serial Control Interface Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Power-Up States PUP Truth Table Power-On Sequence Absolute Maximum Ratings Truth Table Bookmark 24 Bias Voltage Outline Drawing Package Information Pin Descriptions Application Circuit Evaluation PCB List of Materials for Evaluation PCB 116960 - HMC625ALP5 [1]