Datasheet ADL5243 (Analog Devices)

100 MHz to 4000 MHz RF/IF Digitally Controlled VGA Data Sheet ADL5243 FEATURES GENERAL DESCRIPTION Operating frequency from 100 MHz to 4000 MHz
The ADL5243 is a high performance, digitally controlled
Digitally controlled VGA with serial and parallel interfaces
variable gain amplifier operating from 100 MHz to 4000 MHz.
6-bit, 0.5 dB digital step attenuator
The VGA integrates two high performance amplifiers and a
31.5 dB gain control range with ±0.25 dB step accuracy
digital step attenuator (DSA). Amplifier 1 (AMP1) is an
Gain Block Amplifier 1
internally matched gain block amplifier with 20 dB gain, and
Gain: 19.2 dB at 2140 MHz
Amplifier 2 (AMP2) is a broadband ¼ W driver amplifier that
OIP3: 40.2 dBm at 2140 MHz
requires very few external tuning components. The DSA is 6-bit
P1dB: 19.8 dBm at 2140 MHz
with a 31.5 dB gain control range, 0.5 dB steps, and ±0.25 dB
Noise figure: 2.9 dB at 2140 MHz
step accuracy. The attenuation of the DSA can be controlled
¼ W Driver Amplifier 2
using a serial or parallel interface.
Gain: 14.2 dB at 2140 MHz OIP3: 41.1 dBm at 2140 MHz
The gain block and DSA are internally matched to 50 Ω at their
P1dB: 26.0 dBm at 2140 MHz
inputs and outputs, and all three internal devices are separately
Noise figure: 3.7 dB at 2140 MHz
biased. The separate bias allows all or part of the ADL5243 to be
Gain block, DSA, or ¼ W driver amplifier can be first
used, which allows for easy reuse throughout a design. The
Low quiescent current of 175 mA
pinout of the ADL5243 also enables the gain block, DSA, or
The companion ADL5240 i ntegrates a gain block with DSA
¼ W driver amplifier to be first, giving the VGA maximum flexibility in a signal chain.
APPLICATIONS
The ADL5243 consumes 175 mA and operates off a single
Wireless infrastructure
supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a
Automated test equipment
thermally efficient, 5 mm × 5 mm, 32-lead LFCSP and is fully
RF/IF gain control
specified for operation from −40°C to +85°C. A fully populated evaluation board is available.
FUNCTIONAL BLOCK DIAGRAM A K E CL DAT L SEL D0/ D1/ D2/ D3 D4 D5 D6 32 31 30 29 28 27 26 25 VDD 1 24 VDD SERIAL/PARALLEL INTERFACE NC 2 23 NC NC 3 22 NC DSAIN 4 21 DSAOUT 0.5dB 1dB 2dB 4dB 8dB 16dB NC 5 20 NC ADL5243 AMP1OUT/VCC 6 19 AMP2IN NC 7 AMP2 18 NC AMP1 NC 8 17 NC 9 10 11 12 13 14 15 16 N NC 1I NC NC NC NC AS P CC2 BI /V V AM UT
001
2O P
09431-
AM
Figure 1.
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Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Applications Information Basic Layout Connections Amplifier 1 Power Supply Amplifier 1 RF Input Interface Amplifier 1 RF Output Interface Amplifier 2 Power Supply Amplifier 2 RF Input Interface Amplifier 2 RF Output Interface DSA RF Input Interface DSA RF Output Interface DSA SPI Interface SPI Timing SPI Timing Sequence ADL5243 Amplifier 2 Matching ADL5243 Loop Performance Proper Driving Level for the Optimum ACLR Thermal Considerations Soldering Information and Recommended PCB Land Pattern Evaluation Board Outline Dimensions Ordering Guide