Datasheet RX65N, RX651 Groups (Renesas) - 9

link to page 11 link to page 11 RX65N Group, RX651 Group 1. Overview
Table 1.1 Outline of Specifications (8/10) Classification Module/Function Description
SD host interface (SDHI)*3 1 channel Transfer speed: Supports high-speed mode (25 MB/s) and default speed mode (12.5 MB/s) One interface for SD memory and I/O cards (supporting 1- and 4-bit SD buses) SD specifications Part 1: Physical Layer Specification Ver. 3.01 compliant (DDR not supported) Part E1: SDIO Specification Ver. 3.00 Error checking: CRC7 for commands and CRC16 for data Interrupt requests: Card access interrupt, SDIO access interrupt, card detection interrupt, SD buffer access interrupt DMA transfer requests: SD_BUF write and SD_BUF read Support for card detection and write protection SD slave interface (SDSI)*3 1 channel Compliant with the SDIO Card Specification Ver.2.00 (CSA is not supported) 1-bit SD/4-bit SD/SPI mode SDIO Proprietary command is supported SD/SPI Mandatory command is supported Interrupt requests: 6 MMC host interface (MMCIF) 1 channel Transfer speed: Data transfer mode (30 MB/s), backward compatible mode (25 MB/s) Compliant with JEDEC STANDARD JESD84-A441 (DDR is not supported) Interface for Multimedia Cards (MMCs) Device buses: Support for 1-, 4-, and 8-bit MMC buses Interrupt requests: Card detection interrupt, error/timeout interrupt, normal operation interrupt, MMCIF buffer access interrupt DMA transfer requests: CE_DATA write and CE_DATA read Support for card detection, boot operation, high priority interrupt (HPI) Parallel data capture unit (PDC) 1 channel Acquisition of synchronization through external 8-bit horizontal and vertical synchronization signals Setting of the image size when clipping of the output for a one-frame image is required Graphic-LCD controller (GLCDC) 1 channel Various data formats and LCD panels are supported Superposition of 3 planes (single-color background, graphic 1, graphic 2) 32- and 16-bpp graphics data and 8-, 4-, and 1-bit CLUT data formats are supported 2D drawing engine (DRW2D) 1 channel Vector drawing (straight lines, triangles, and circles) Bit blitting (with support for filling, copying, stretching, and rotation) Bus master function for input and output of frame buffer data 32-, 16-, and 8-bit pixel graphics data are supported Bus master function for input of texture data Input of texture data (32, 24, 16, 8, 4, 2, or 1 bit) are supported. Run length encoding is supported A CLUT is installed and index data can be converted into color data Two rendering modes are supported (register mode and display list mode) Performance counting Interrupts in response to completion of rendering and processing of the display list R01DS0276EJ0230 Rev.2.30 Page 9 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice