Datasheet ADP5071 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | 2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs |
| 页数 / 页 | 27 / 2 — ADP5071. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 7/2019—Rev. D … |
| 修订版 | E |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
ADP5071. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 7/2019—Rev. D to Rev. E. 3/2019—Rev. C to Rev. D. 6/2018—Rev. B to Rev. C
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ADP5071 Data Sheet TABLE OF CONTENTS
Features .. 1 Soft Start .. 15 Applications ... 1 Slew Rate Control ... 15 Typical Application Circuit ... 1 Current-Limit Protection .. 15 General Description ... 1 Overvoltage Protection .. 15 Revision History ... 2 Thermal Shutdown .. 15 Specifications ... 3 Start-Up Sequence .. 15 Absolute Maximum Ratings .. 5 Applications Information .. 17 Thermal Resistance .. 5 ADIsimPower Design Tool ... 17 ESD Caution .. 5 Component Selection .. 17 Pin Configurations and Function Descriptions ... 6 Loop Compensation .. 20 Typical Performance Characteristics ... 8 Common Applications .. 22 Theory of Operation .. 14 Super Low Noise With Optional LDOs... 24 PWM Mode ... 14 SEPIC Step-Up/Step-Down Operation ... 25 PSM Mode ... 14 Layout Considerations ... 26 Undervoltage Lockout (UVLO) ... 14 Outline Dimensions ... 27 Oscillator and Synchronization .. 14 Ordering Guide .. 27 Internal Regulators ... 14 Precision Enabling .. 15
REVISION HISTORY 7/2019—Rev. D to Rev. E
Change to Pull-Down Resistance Parameter, Table 2 ... 3 Replaced Figure 7 ... 8 Changes to Table 3 and Table 4 ... 5 Added Figure 3, Renumbered Sequentially ... 6
3/2019—Rev. C to Rev. D
Changes to Figure 37 Caption to Figure 39 Caption ... 13 Changes to Figure 48 .. 24 Changes to Internal Regulators Section .. 14 Change to Soft Start Section ... 15
6/2018—Rev. B to Rev. C
Changes to Component Selection Section .. 17 Changes to Figure 34, Figure 35, and Figure 36 ... 13 Changes to Output Capacitors Section, Soft Start Resistor Section, and Diodes Section ... 18
7/2017—Rev. A to Rev. B
Changes to Figure 52 Caption .. 26 Changes to Table 10 and Table 11 .. 23 Added Figure 53 ... 26 Updated Outline Dimensions ... 27 Updated Outline Dimensions ... 27 Changes to Ordering Guide .. 27 Changes to Ordering Guide .. 27
6/2015—Rev. 0 to Rev. A 2/2015—Revision 0: Initial Version
Added 20-Lead TSSOP .. Universal Rev. E | Page 2 of 27 Document Outline Features Applications Typical Application Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation PWM Mode PSM Mode Undervoltage Lockout (UVLO) Oscillator and Synchronization Internal Regulators Precision Enabling Soft Start Slew Rate Control Current-Limit Protection Overvoltage Protection Thermal Shutdown Start-Up Sequence Applications Information ADIsimPower Design Tool Component Selection Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator Loop Compensation Boost Regulator Inverting Regulator Common Applications Super Low Noise With Optional LDOs SEPIC Step-Up/Step-Down Operation Layout Considerations Outline Dimensions Ordering Guide
ADP5071 Data Sheet TABLE OF CONTENTS
Features .. 1 Soft Start .. 15 Applications ... 1 Slew Rate Control ... 15 Typical Application Circuit ... 1 Current-Limit Protection .. 15 General Description ... 1 Overvoltage Protection .. 15 Revision History ... 2 Thermal Shutdown .. 15 Specifications ... 3 Start-Up Sequence .. 15 Absolute Maximum Ratings .. 5 Applications Information .. 17 Thermal Resistance .. 5 ADIsimPower Design Tool ... 17 ESD Caution .. 5 Component Selection .. 17 Pin Configurations and Function Descriptions ... 6 Loop Compensation .. 20 Typical Performance Characteristics ... 8 Common Applications .. 22 Theory of Operation .. 14 Super Low Noise With Optional LDOs... 24 PWM Mode ... 14 SEPIC Step-Up/Step-Down Operation ... 25 PSM Mode ... 14 Layout Considerations ... 26 Undervoltage Lockout (UVLO) ... 14 Outline Dimensions ... 27 Oscillator and Synchronization .. 14 Ordering Guide .. 27 Internal Regulators ... 14 Precision Enabling .. 15
REVISION HISTORY 7/2019—Rev. D to Rev. E
Change to Pull-Down Resistance Parameter, Table 2 ... 3 Replaced Figure 7 ... 8 Changes to Table 3 and Table 4 ... 5 Added Figure 3, Renumbered Sequentially ... 6
3/2019—Rev. C to Rev. D
Changes to Figure 37 Caption to Figure 39 Caption ... 13 Changes to Figure 48 .. 24 Changes to Internal Regulators Section .. 14 Change to Soft Start Section ... 15
6/2018—Rev. B to Rev. C
Changes to Component Selection Section .. 17 Changes to Figure 34, Figure 35, and Figure 36 ... 13 Changes to Output Capacitors Section, Soft Start Resistor Section, and Diodes Section ... 18
7/2017—Rev. A to Rev. B
Changes to Figure 52 Caption .. 26 Changes to Table 10 and Table 11 .. 23 Added Figure 53 ... 26 Updated Outline Dimensions ... 27 Updated Outline Dimensions ... 27 Changes to Ordering Guide .. 27 Changes to Ordering Guide .. 27
6/2015—Rev. 0 to Rev. A 2/2015—Revision 0: Initial Version
Added 20-Lead TSSOP .. Universal Rev. E | Page 2 of 27 Document Outline Features Applications Typical Application Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation PWM Mode PSM Mode Undervoltage Lockout (UVLO) Oscillator and Synchronization Internal Regulators Precision Enabling Soft Start Slew Rate Control Current-Limit Protection Overvoltage Protection Thermal Shutdown Start-Up Sequence Applications Information ADIsimPower Design Tool Component Selection Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator Loop Compensation Boost Regulator Inverting Regulator Common Applications Super Low Noise With Optional LDOs SEPIC Step-Up/Step-Down Operation Layout Considerations Outline Dimensions Ordering Guide