Datasheet ADP5071 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs |
| 页数 / 页 | 27 / 10 — ADP5071. Data Sheet. 100. NCY. ICI. TA = +125°C. TA = +25°C. TA = –40°C. … |
| 修订版 | E |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
ADP5071. Data Sheet. 100. NCY. ICI. TA = +125°C. TA = +25°C. TA = –40°C. 0.001. 0.01. 0.1. LOAD (A). 0.5. 0.3. INAL. –0.1. N F. ARI. –0.3. VOUT ACCURACY
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ADP5071 Data Sheet 100 100 80 80 %) %) ( 60 ( 60 NCY NCY E E ICI ICI F 40 F 40 F F E E 20 20 TA = +125°C TA = +125°C TA = +25°C TA = +25°C TA = –40°C TA = –40°C 0 0 0.001 0.01 0.1 1
015
0.001 0.01 0.1 1
018
LOAD (A)
12069-
LOAD (A)
12069- Figure 16. Boost Regulator Efficiency over Temperature, Figure 19. Inverting Regulator Efficiency over Temperature, VIN = 5 V, VPOS = 15 V, fSW = 1.2 MHz VIN = 5 V, VNEG = −15 V, fSW = 1.2 MHz
0.5 0.5 0.3 %) 0.3 %) ( ( INAL INAL M M 0.1 0.1 NO NO M M RO RO –0.1 N F –0.1 N F IO IO AT AT ARI –0.3 ARI V –0.3 V VOUT ACCURACY VOUT ACCURACY VREF ACCURACY VFB1 ACCURACY VFB2 ACCURACY –0.5 –0.5 0 5 10 15 20
016
0 5 10 15 20
019
VIN (V) V
12069-
IN (V)
12069- Figure 17. Boost Regulator Line Regulation, VPOS = 15 V, Figure 20. Inverting Regulator Line Regulation, VNEG = −15 V, fSW = 1.2 MHz, 15 mA Load, TA = 25°C fSW = 1.2 MHz, 15 mA Load, TA = 25°C
0.5 0.5 %) %) ( ( B1 B2 F 0.3 F 0.3 N V N V I I E E 0.1 0.1 CHANG CHANG N, N, IO IO –0.1 –0.1 AT AT UL UL G G –0.3 –0.3 AD RE AD RE O O L 1.2MHz L 1.2MHz 2.4MHz 2.4MHz –0.5 –0.5 0 0.1 0.2 0.3 0.4 0.5
017
0 0.05 0.10 0.15
020
LOAD (A)
12069-
LOAD (A)
12069- Figure 18. Boost Regulator Load Regulation, VIN = 5 V, VPOS = 15 V Figure 21. Inverting Regulator Load Regulation, VIN = 5 V, VNEG = −15 V Rev. E | Page 10 of 27 Document Outline Features Applications Typical Application Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation PWM Mode PSM Mode Undervoltage Lockout (UVLO) Oscillator and Synchronization Internal Regulators Precision Enabling Soft Start Slew Rate Control Current-Limit Protection Overvoltage Protection Thermal Shutdown Start-Up Sequence Applications Information ADIsimPower Design Tool Component Selection Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator Loop Compensation Boost Regulator Inverting Regulator Common Applications Super Low Noise With Optional LDOs SEPIC Step-Up/Step-Down Operation Layout Considerations Outline Dimensions Ordering Guide
015
0.001 0.01 0.1 1
018
LOAD (A)
12069-
LOAD (A)
12069- Figure 16. Boost Regulator Efficiency over Temperature, Figure 19. Inverting Regulator Efficiency over Temperature, VIN = 5 V, VPOS = 15 V, fSW = 1.2 MHz VIN = 5 V, VNEG = −15 V, fSW = 1.2 MHz
0.5 0.5 0.3 %) 0.3 %) ( ( INAL INAL M M 0.1 0.1 NO NO M M RO RO –0.1 N F –0.1 N F IO IO AT AT ARI –0.3 ARI V –0.3 V VOUT ACCURACY VOUT ACCURACY VREF ACCURACY VFB1 ACCURACY VFB2 ACCURACY –0.5 –0.5 0 5 10 15 20
016
0 5 10 15 20
019
VIN (V) V
12069-
IN (V)
12069- Figure 17. Boost Regulator Line Regulation, VPOS = 15 V, Figure 20. Inverting Regulator Line Regulation, VNEG = −15 V, fSW = 1.2 MHz, 15 mA Load, TA = 25°C fSW = 1.2 MHz, 15 mA Load, TA = 25°C
0.5 0.5 %) %) ( ( B1 B2 F 0.3 F 0.3 N V N V I I E E 0.1 0.1 CHANG CHANG N, N, IO IO –0.1 –0.1 AT AT UL UL G G –0.3 –0.3 AD RE AD RE O O L 1.2MHz L 1.2MHz 2.4MHz 2.4MHz –0.5 –0.5 0 0.1 0.2 0.3 0.4 0.5
017
0 0.05 0.10 0.15
020
LOAD (A)
12069-
LOAD (A)
12069- Figure 18. Boost Regulator Load Regulation, VIN = 5 V, VPOS = 15 V Figure 21. Inverting Regulator Load Regulation, VIN = 5 V, VNEG = −15 V Rev. E | Page 10 of 27 Document Outline Features Applications Typical Application Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation PWM Mode PSM Mode Undervoltage Lockout (UVLO) Oscillator and Synchronization Internal Regulators Precision Enabling Soft Start Slew Rate Control Current-Limit Protection Overvoltage Protection Thermal Shutdown Start-Up Sequence Applications Information ADIsimPower Design Tool Component Selection Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator Loop Compensation Boost Regulator Inverting Regulator Common Applications Super Low Noise With Optional LDOs SEPIC Step-Up/Step-Down Operation Layout Considerations Outline Dimensions Ordering Guide