Preliminary Datasheet P9415 (IDT) - 9

P9415 Preliminary Datasheet
Symbol Description Conditions Min Typ Max Units
Capacitance VIL Input Threshold Low 0.7 V VIH Input Threshold High 1.4 V V = 0 V and 1.8 V, pull-ups ILKG Input Leakage Current -1 1 µA disabled VOL Output Logic Low IOL= 3mA 0.36 V
Notes:
1. VRECT may exceed 20.5 V, but the device EC table limits are not guaranteed under this condition. 2. Input Voltage Operating Range is dependent upon the type of Transmitter Power Stage (ful -bridge, half-bridge) and Transmitting Coil Inductance. WPC Specifications should be consulted for appropriate input voltage ranges by end product type. 3. Do not external y load. For internal biasing only. 4. Guaranteed by design and not subject to 100% production testing. 5. Full power transfer wil not occur at the minimum IC operating specification. 6. LDO1P8 pin can only be loaded as shown in reference schematics. 7. Any open-drain GPIO pin (SCL, SDA, OD2, OD3, OD4) that is connected as an input to the ADC should stay below 2.1V to prevent saturation of the ADC, and any push-pul GPIO pin (GP0, GP1, GP2, GP3, GP4, GP5, GP6) connected to the ADC, the voltage must be ≤LDO1P8 to avoid interference with the LDO1P8 power supply. 8. The test condition is up to 55oC. © 2019 IDT  A Renesas Company. 9 Revision 0.8 August 29, 2019